ScanCamouflage: Obfuscating Scan Chains with Camouflaged Sequential and Logic Gates

Tarik Ibrahimpasic, Grace Li Zhang, Michaela Brunner, Georg Sigl, Bing Li, Ulf Schlichtmann

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Scan chain is a commonly used technique in testing integrated circuits as it provides observability and controllability of the internal states of circuits. However, its presence can make circuits vulnerable to attacks and potentially result in confidential internal data leakage. In this paper, we propose a novel technique for obfuscating scan chains using camouflaged flip-flops, which are designed with the same layout as the original flip-flops but have the actual functionality of a buffer. Furthermore, we employ camouflaged logic gates interconnected in special configurations to increase the difficulty of SAT attack. Experimental results demonstrate that circuits with only a small number of flip-flops can already be protected by the proposed technique while incurring only a minimal area overhead.

Original languageEnglish
Title of host publication2024 Design, Automation and Test in Europe Conference and Exhibition, DATE 2024 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350348590
StatePublished - 2024
Event2024 Design, Automation and Test in Europe Conference and Exhibition, DATE 2024 - Valencia, Spain
Duration: 25 Mar 202427 Mar 2024

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591

Conference

Conference2024 Design, Automation and Test in Europe Conference and Exhibition, DATE 2024
Country/TerritorySpain
CityValencia
Period25/03/2427/03/24

Keywords

  • gate camouflage
  • scan chain obfuscation

Fingerprint

Dive into the research topics of 'ScanCamouflage: Obfuscating Scan Chains with Camouflaged Sequential and Logic Gates'. Together they form a unique fingerprint.

Cite this