Scalable fabrication of metallic nanogaps using CMOS-based 10 nm spacer lithography

Domenikos Chryssikos, Martin Heigl, Evanthia Kounoupioti, Karl Neumeier, Robert Wieland, Marc Tornow

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Constant progress in nanofabrication has been one of the main enablers of Moore's law. However, most state-of-the-art laboratory nanofabrication techniques suffer from poor scalability and low throughput. In this work, we present, as a proof of concept, the fabrication of a ∼10 nm wide and ∼45-50 nm tall silicon nitride spacer, which is then used to define nanogaps in a subsequently evaporated Cr/Au top layer. The entire process is scalable, and the spacer fabrication process is compatible with complementary metal-oxide-semiconductor (CMOS) technology, relying on established deposition and etching techniques. Our introduced nanopatterning technique may lend itself to becoming an attractive, cost-efficient alternative to common nanolithographic techniques for applications in nanoelectronics, nanophotonics and nanoscale sensing.

Original languageEnglish
Title of host publication2022 IEEE 22nd International Conference on Nanotechnology, NANO 2022
PublisherIEEE Computer Society
Pages234-237
Number of pages4
ISBN (Electronic)9781665452250
DOIs
StatePublished - 2022
Event22nd IEEE International Conference on Nanotechnology, NANO 2022 - Palma de Mallorca, Spain
Duration: 4 Jul 20228 Jul 2022

Publication series

NameProceedings of the IEEE Conference on Nanotechnology
Volume2022-July
ISSN (Print)1944-9399
ISSN (Electronic)1944-9380

Conference

Conference22nd IEEE International Conference on Nanotechnology, NANO 2022
Country/TerritorySpain
CityPalma de Mallorca
Period4/07/228/07/22

Fingerprint

Dive into the research topics of 'Scalable fabrication of metallic nanogaps using CMOS-based 10 nm spacer lithography'. Together they form a unique fingerprint.

Cite this