Scalable fabrication of metallic nanogaps using CMOS-based 10 nm spacer lithography

Constant progress in nanofabrication has been one of the main enablers of Moore's law. However, most state-of-the-art laboratory nanofabrication techniques suffer from poor scalability and low throughput. In this work, we present, as a proof of concept, the fabrication of a ∼10 nm wide and ∼45-50 nm tall silicon nitride spacer, which is then used to define nanogaps in a subsequently evaporated Cr/Au top layer. The entire process is scalable, and the spacer fabrication process is compatible with complementary metal-oxide-semiconductor (CMOS) technology, relying on established deposition and etching techniques. Our introduced nanopatterning technique may lend itself to becoming an attractive, cost-efficient alternative to common nanolithographic techniques for applications in nanoelectronics, nanophotonics and nanoscale sensing.