TY - GEN
T1 - Scalable design for field-coupled nanocomputing circuits
AU - Walter, Marcel
AU - Wille, Robert
AU - Torres, Frank Sill
AU - Große, Daniel
AU - Drechsler, Rolf
N1 - Publisher Copyright:
© 2019 Copyright is held by the owner/author(s). Publication rights licensed to ACM.
PY - 2019/1/21
Y1 - 2019/1/21
N2 - Field-coupled Nanocomputing (FCN) technologies are considered as a solution to overcome physical boundaries of conventional CMOS approaches. But despite ground breaking advances regarding their physical implementation as e. g. Quantum-dot Cellular Automata (QCA), Nanomagnet Logic (NML), and many more, there is an unsettling lack of methods for large-scale design automation of FCN circuits. In fact, design automation for this class of technologies still is in its infancy - heavily relying either on manual labor or automatic methods which are applicable for rather small functionality only. This work presents a design method which - for the first time - allows for the scalable design of FCN circuits that satisfy dedicated constraints of these technologies. The proposed scheme is capable of handling around 40 000 gates within seconds while the current state-of-the-art takes hours to handle around 20 gates. This is confirmed by experimental results on the layout level for various established benchmarks libraries.
AB - Field-coupled Nanocomputing (FCN) technologies are considered as a solution to overcome physical boundaries of conventional CMOS approaches. But despite ground breaking advances regarding their physical implementation as e. g. Quantum-dot Cellular Automata (QCA), Nanomagnet Logic (NML), and many more, there is an unsettling lack of methods for large-scale design automation of FCN circuits. In fact, design automation for this class of technologies still is in its infancy - heavily relying either on manual labor or automatic methods which are applicable for rather small functionality only. This work presents a design method which - for the first time - allows for the scalable design of FCN circuits that satisfy dedicated constraints of these technologies. The proposed scheme is capable of handling around 40 000 gates within seconds while the current state-of-the-art takes hours to handle around 20 gates. This is confirmed by experimental results on the layout level for various established benchmarks libraries.
UR - http://www.scopus.com/inward/record.url?scp=85061138693&partnerID=8YFLogxK
U2 - 10.1145/3287624.3287705
DO - 10.1145/3287624.3287705
M3 - Conference contribution
AN - SCOPUS:85061138693
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 197
EP - 202
BT - ASP-DAC 2019 - 24th Asia and South Pacific Design Automation Conference
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 24th Asia and South Pacific Design Automation Conference, ASPDAC 2019
Y2 - 21 January 2019 through 24 January 2019
ER -