TY - GEN
T1 - Saving potentials of adiab. logic on system level
T2 - 12th International Symposium on Integrated Circuits, ISIC-2009
AU - Teichmann, Philip
AU - Vollmer, Marius
AU - Fischer, Jürgen
AU - Heyne, Benjamin
AU - Götze, Jürgen
AU - Schmitt-Landsiedel, Doris
PY - 2009
Y1 - 2009
N2 - The energy consumption of digital systems can be greatly reduced by applying Adiabatic Logic (AL). Making best use of AL requires a dedicated system design regarding the inherent characteristics of AL. In this paper we investigate the CORDIC architecture, that can be used for various signal processing algorithms and is preeminently suitable for AL. For fast functional testing, we propose a methodology to describe AL in VHDL. An adiabatic CORDIC-based DCT is used as a test vehicle to demonstrate on system level the applicability of AL for ultra-low-power digital signal processing. We present an estimation method for the energy consumption and therewith compare a variety of static CMOS implementations of the DCT to our adiabatic DCT. The estimation results are verified by simulating the whole system in a 130nm CMOS technology for various supply voltages. Even at a low supply voltage of 0.8V the adiabatic DCT's energy consumption is less than 15% compared to the static CMOS implementation.
AB - The energy consumption of digital systems can be greatly reduced by applying Adiabatic Logic (AL). Making best use of AL requires a dedicated system design regarding the inherent characteristics of AL. In this paper we investigate the CORDIC architecture, that can be used for various signal processing algorithms and is preeminently suitable for AL. For fast functional testing, we propose a methodology to describe AL in VHDL. An adiabatic CORDIC-based DCT is used as a test vehicle to demonstrate on system level the applicability of AL for ultra-low-power digital signal processing. We present an estimation method for the energy consumption and therewith compare a variety of static CMOS implementations of the DCT to our adiabatic DCT. The estimation results are verified by simulating the whole system in a 130nm CMOS technology for various supply voltages. Even at a low supply voltage of 0.8V the adiabatic DCT's energy consumption is less than 15% compared to the static CMOS implementation.
UR - http://www.scopus.com/inward/record.url?scp=77950434603&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:77950434603
SN - 9789810824686
T3 - ISIC-2009 - 12th International Symposium on Integrated Circuits, Proceedings
SP - 105
EP - 108
BT - ISIC-2009 - 12th International Symposium on Integrated Circuits, Proceedings
Y2 - 14 December 2009 through 16 December 2009
ER -
