TY - GEN
T1 - Runtime adaptation of application execution under thermal and power constraints in massively parallel processor arrays
AU - Sousa, Éricles
AU - Hannig, Frank
AU - Teich, Jürgen
AU - Chen, Qingqing
AU - Schlichtmann, Ulf
N1 - Publisher Copyright:
© 2015 ACM.
PY - 2015/6/1
Y1 - 2015/6/1
N2 - Massively Parallel Processor Arrays (MPPAs) can be nicely used in portable devices such as tablets and smartphones. However, applications running on mobile platforms require a certain performance level or quality (e.g., high-resolution image processing) that need to be satisfied while adhering to a certain power budget and temperature threshold. As a solution to the aforementioned challenges, we consider a resource-aware computing paradigm to exploit runtime adaptation without violating any thermal and/or power constraint in a programmable MPPA. For estimating the power consumption, we developed a mathematical model based on the post-synthesis implementation of an MPPA in different CMOS technologies while the temperature variation was emulated. We showcase our hardware/software mechanism to load new, on-the-fly configurations into the accelerator, considering quality/throughput tradeoffs for image processing applications. The results show that the average power consumption of a Sobel and Laplace operators using different number of processing elements amounts to 1.24mW and 10.35mW, respectively. Furthermore, only 1.64 μs are necessary for configuring a class of MPPA running at 550 MHz.
AB - Massively Parallel Processor Arrays (MPPAs) can be nicely used in portable devices such as tablets and smartphones. However, applications running on mobile platforms require a certain performance level or quality (e.g., high-resolution image processing) that need to be satisfied while adhering to a certain power budget and temperature threshold. As a solution to the aforementioned challenges, we consider a resource-aware computing paradigm to exploit runtime adaptation without violating any thermal and/or power constraint in a programmable MPPA. For estimating the power consumption, we developed a mathematical model based on the post-synthesis implementation of an MPPA in different CMOS technologies while the temperature variation was emulated. We showcase our hardware/software mechanism to load new, on-the-fly configurations into the accelerator, considering quality/throughput tradeoffs for image processing applications. The results show that the average power consumption of a Sobel and Laplace operators using different number of processing elements amounts to 1.24mW and 10.35mW, respectively. Furthermore, only 1.64 μs are necessary for configuring a class of MPPA running at 550 MHz.
UR - https://www.scopus.com/pages/publications/84959460825
U2 - 10.1145/2764967.2771933
DO - 10.1145/2764967.2771933
M3 - Conference contribution
AN - SCOPUS:84959460825
T3 - Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2015
SP - 121
EP - 124
BT - Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2015
A2 - Stuijk, Sander
PB - Association for Computing Machinery, Inc
T2 - 18th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2015
Y2 - 1 June 2015 through 3 June 2015
ER -