Robustness test of CMOS circuit based on its worst case power consumption signature using ATE and GA-MIE technique

This paper presents a diagnosis method which works with industrial semiconductor ATE for analyzing the robustness of the circuit and uses genetic algorithm (GA) with a novel multiple individuals (chromosomes) evolution (GA-MIE) technique. The term robustness in this paper refers to stability and performance of circuits with multiple sources of uncertainties. The objective is studying the worst case activity on chip based on its worst case power consumption signature with respect to a set of worst case input tests. Tests are referred to input patterns and test conditions, since the activity of CMOS circuit is a complex function of the input tests and operating parameters. For instance, the timing and voltage levels on chip can vary due to a small variation of input timing and voltage level. Traditional test and analysis approaches do not consider test condition variation. Experimental results on a test chip show the worst case active tests generated with our approach provoke the device to run slower than normal tests using typical approaches.