RISC-V Triplet: Tapeouts for Security Applications

In 2019 we started to design RISC-V based ASICs including security IP with a focus on Post Quantum Cryptography (PQC) at our institute. The primary goal were small, resource efficient implementations with high flexibility through HW/SW-codesign. In a first ASIC we included tightly coupled PQC accelerators directly integrated in a 32 bit RISC-V processor. We achieved speedups and power savings of a factor 10 for many lattice based PQC algorithms. Furthermore, this design included HW-Trojans to demonstrate the risk of such attacks and to perform research on Trojan detection techniques. In a second ASIC we went for loosely coupled accelerators optimizing bus integration. We also included accelerators for isogeny based PQC and code based cryptography. Furthermore higher frequency and a smaller technology was used. The underlying idea was to get experience for chip design with the first tapeout on a 65 nm technology and use this for the second tapeout in a 22 nm technology with a more challenging design flow. The third step remained in the same technology but went from a simple RISCV platform to a complex security platform provided by the OpenTitan open-source project. The target here was to modify this platform in such a way that key storage can be achieved with Physical Unclonable Functions (PUFs) and PQC enhancements are included in the big number processor. With these ASICs we enable deeper security analysis of implementations in our hardware lab. The first chip was, e.g., given to a reverse engineering lab to reconstruct the netlist from the silicon and to find the Trojans. Additionally, the chip design activities educate students and PhD candidates addressing the needs of the industry in more skilled people.