Retiming of Synchronous Circuits with Variable Topology

Generally, circuit design leads to a trade-off scenario between speed and various parameters lake power dissapalion, AT complexity, re-use of already existing cells, design time, etc. To deal with this trade-off, the interaction between retiming and the selection of combinational elements from a set of cells with these different parameters is considered here. Additionally, modifications of the circuat graph concerning the interconnections, e.g. due to associativity of the underlying algorithm, lead to a parameterized topology. The algorithm presented in this paper combines all three, retiming, the selection of specijiic cells and the choice of an appropriate topology an one optimization step.