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Resonant multistage charging of dominant capacitances

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

It has been shown [2] that adiabatic switching can significantly reduce the dynamic power dissipation in an integrated circuit. Due to the overhead in the realization of adiabatic logic blocks [3] the best results are achieved when it is used only for charging dominant loads in an integrated circuit [7]. It has been demonstrated [4] that a multi stage driver is needed for minimal power dissipation. In this article a complete three stage driver including the generation of oscillating supply is described. To obtain a minimal power dissipation during synchronization the resonant frequency has to be constant. Therefore the waveforms for the logic states of the signal and the realization of a single stage differ from those presented in [4]. In the H-SPICE simulations losses of the inductor are taken into account. This allows to estimate the power reduction that is achievable in a real system.

Original languageEnglish
Title of host publicationIntegrated Circuit Design
Subtitle of host publicationPower and Timing Modeling, Optimization and Simulation - 12th International Workshop, PATMOS 2002, Proceedings
EditorsBertrand Hochet, Antonio J. Acosta, Manuel J. Bellido
PublisherSpringer Verlag
Pages101-107
Number of pages7
ISBN (Print)9783540441434
DOIs
StatePublished - 2002
Event12th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2002 - Seville, Spain
Duration: 11 Sep 200213 Sep 2002

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume2451
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Conference

Conference12th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2002
Country/TerritorySpain
CitySeville
Period11/09/0213/09/02

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