Reliability monitoring of digital circuits by in situ timing measurement

Nasim Pour Aryan; Georg Georgakos; Doris Schmitt-Landsiedel

doi:10.1109/PATMOS.2013.6662168

Reliability monitoring of digital circuits by in situ timing measurement

Nasim Pour Aryan
, Georg Georgakos
, Doris Schmitt-Landsiedel

Medicine and Health

Technical University of Munich
Infineon Technologies AG

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

Recent technological advances in semiconductor industry have led to extreme scaling of CMOS devices. In such advanced technologies fulfilling application specific reliability requirements is not an easy task. This is a crucial issue particularly in case of safety-critical applications with strict reliability requirements. In this paper we propose accurate monitoring of reliability status of digital circuits through measuring the remaining timing slack of the system. Moreover, we propose and evaluate the optimized design and implementation of the required aging resistant circuitry in a low power 65nm technology. Besides the quantitative evaluations regarding the accuracy and robustness of the monitoring circuitry, we evaluate the power efficiency of the monitoring approach for a test circuit. Our studies support the applicability of the proposed monitoring methodology to fulfill application specific reliability requirements.

Original language	English
Title of host publication	2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2013
Publisher	IEEE Computer Society
Pages	150-156
Number of pages	7
ISBN (Print)	9781479911707
DOIs	https://doi.org/10.1109/PATMOS.2013.6662168
State	Published - 2013
Event	2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2013 - Karlsruhe, Germany Duration: 9 Sep 2013 → 11 Sep 2013

Publication series

Name	2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2013

Conference

Conference	2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2013
Country/Territory	Germany
City	Karlsruhe
Period	9/09/13 → 11/09/13

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 9 Industry, Innovation, and Infrastructure

Access to Document

10.1109/PATMOS.2013.6662168

Cite this

Aryan, N. P., Georgakos, G., & Schmitt-Landsiedel, D. (2013). Reliability monitoring of digital circuits by in situ timing measurement. In 2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2013 (pp. 150-156). Article 6662168 (2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2013). IEEE Computer Society. https://doi.org/10.1109/PATMOS.2013.6662168

Aryan, Nasim Pour ; Georgakos, Georg ; Schmitt-Landsiedel, Doris. / Reliability monitoring of digital circuits by in situ timing measurement. 2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2013. IEEE Computer Society, 2013. pp. 150-156 (2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2013).

@inproceedings{23b3fd7a866946c58397235e34b338f3,

title = "Reliability monitoring of digital circuits by in situ timing measurement",

abstract = "Recent technological advances in semiconductor industry have led to extreme scaling of CMOS devices. In such advanced technologies fulfilling application specific reliability requirements is not an easy task. This is a crucial issue particularly in case of safety-critical applications with strict reliability requirements. In this paper we propose accurate monitoring of reliability status of digital circuits through measuring the remaining timing slack of the system. Moreover, we propose and evaluate the optimized design and implementation of the required aging resistant circuitry in a low power 65nm technology. Besides the quantitative evaluations regarding the accuracy and robustness of the monitoring circuitry, we evaluate the power efficiency of the monitoring approach for a test circuit. Our studies support the applicability of the proposed monitoring methodology to fulfill application specific reliability requirements.",

author = "Aryan, \{Nasim Pour\} and Georg Georgakos and Doris Schmitt-Landsiedel",

year = "2013",

doi = "10.1109/PATMOS.2013.6662168",

language = "English",

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series = "2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2013",

publisher = "IEEE Computer Society",

pages = "150--156",

booktitle = "2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2013",

note = "2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2013 ; Conference date: 09-09-2013 Through 11-09-2013",

}

Aryan, NP, Georgakos, G & Schmitt-Landsiedel, D 2013, Reliability monitoring of digital circuits by in situ timing measurement. in 2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2013., 6662168, 2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2013, IEEE Computer Society, pp. 150-156, 2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2013, Karlsruhe, Germany, 9/09/13. https://doi.org/10.1109/PATMOS.2013.6662168

Reliability monitoring of digital circuits by in situ timing measurement. / Aryan, Nasim Pour; Georgakos, Georg; Schmitt-Landsiedel, Doris.
2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2013. IEEE Computer Society, 2013. p. 150-156 6662168 (2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2013).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

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N2 - Recent technological advances in semiconductor industry have led to extreme scaling of CMOS devices. In such advanced technologies fulfilling application specific reliability requirements is not an easy task. This is a crucial issue particularly in case of safety-critical applications with strict reliability requirements. In this paper we propose accurate monitoring of reliability status of digital circuits through measuring the remaining timing slack of the system. Moreover, we propose and evaluate the optimized design and implementation of the required aging resistant circuitry in a low power 65nm technology. Besides the quantitative evaluations regarding the accuracy and robustness of the monitoring circuitry, we evaluate the power efficiency of the monitoring approach for a test circuit. Our studies support the applicability of the proposed monitoring methodology to fulfill application specific reliability requirements.

AB - Recent technological advances in semiconductor industry have led to extreme scaling of CMOS devices. In such advanced technologies fulfilling application specific reliability requirements is not an easy task. This is a crucial issue particularly in case of safety-critical applications with strict reliability requirements. In this paper we propose accurate monitoring of reliability status of digital circuits through measuring the remaining timing slack of the system. Moreover, we propose and evaluate the optimized design and implementation of the required aging resistant circuitry in a low power 65nm technology. Besides the quantitative evaluations regarding the accuracy and robustness of the monitoring circuitry, we evaluate the power efficiency of the monitoring approach for a test circuit. Our studies support the applicability of the proposed monitoring methodology to fulfill application specific reliability requirements.

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DO - 10.1109/PATMOS.2013.6662168

M3 - Conference contribution

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BT - 2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2013

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Y2 - 9 September 2013 through 11 September 2013

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Aryan NP, Georgakos G, Schmitt-Landsiedel D. Reliability monitoring of digital circuits by in situ timing measurement. In 2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2013. IEEE Computer Society. 2013. p. 150-156. 6662168. (2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2013). doi: 10.1109/PATMOS.2013.6662168

Reliability monitoring of digital circuits by in situ timing measurement

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