Reliability-driven voltage optimization for NCFET-based SRAM memory banks

Victor M. Van Santen, Simon Thomann, Yogesh S. Chauchan, Jorg Henkel, Hussam Amrouch

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations


Negative Capacitance Field-Effect Transistors (NCFET) are promising significant power reductions while maintaining performance due to their internal voltage amplification. However, the addition of the ferroelectric layer also introduces a higher gate capacitance, which has to be charged and discharged resulting in higher power consumption. This results in trade-offs when employing NC-FinFET with respect to the thickness of the ferroelectric layer and their operating voltage on power, performance and reliability in circuits. This design-space is currently not explored, as existing research focused on a transistor-to-transistor comparison to show the superiority of NC-FinFET at the same voltage. In this work, we evaluate NC-FinFET employment in a full SRAM memory array (including write driver, sense amplifier, pre-charging, etc.) to obtain circuit delay, read and hold power and reliability metrics. This work shows, that solely evaluating SRAM cells results in inaccurate delay and power estimations compared to a full SRAM array. We explore iso-voltage and iso-performance NC-FinFET operation. Additionally, we explore two new operation modes: operating NC-FinFET within the same overall power consumption (iso-power) and operating at the same noise margins (iso-reliability). This exploration shows, for the first time, how ferroelectric layer thickness plays a role on reliability as a 4 nm layer features a 47% loss compared to FinFET. Lastly, we obtain the activity of a register file in a processor simulator to obtain the ultimate impact on power and energy consumption of employing NC-FinFET in a microprocessor.

Original languageEnglish
Title of host publicationProceedings - 2021 IEEE 39th VLSI Test Symposium, VTS 2021
PublisherIEEE Computer Society
ISBN (Electronic)9781665419499
StatePublished - 25 Apr 2021
Externally publishedYes
Event39th IEEE VLSI Test Symposium, VTS 2021 - San Diego, United States
Duration: 26 Apr 202128 Apr 2021

Publication series

NameProceedings of the IEEE VLSI Test Symposium


Conference39th IEEE VLSI Test Symposium, VTS 2021
Country/TerritoryUnited States
CitySan Diego


  • Circuit Reliability
  • Delay
  • Energy
  • FinFET
  • Memory
  • Performance
  • Power
  • SRAM


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