Reliability analysis of digital circuits considering intrinsic noise

Veit B. Kleeberger, Ulf Schlichtmann

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

The scaling of digital CMOS circuits into the nanometer region causes an increase in intrinsic device noise. Existing methods to analyze the impact of noise on circuit performance use analytical estimations based on simplified cell models. In this paper we propose a characterization method for the impact of intrinsic noise based on SPICE simulation. The method considers all major noise sources in integrated circuits and is able to determine the effect of intrinsic noise on circuit reliability. Contrary to existing methods, it is general enough to analyze different logic implementation styles and device technologies. Additionally it is shown that previous methods overestimate the influence of intrinsic noise up to a factor of 4.

Original languageEnglish
Title of host publicationProceedings of the 3rd Asia Symposium on Quality Electronic Design, ASQED 2011
Pages167-173
Number of pages7
DOIs
StatePublished - 2011
Event3rd Asia Symposium on Quality Electronic Design, ASQED 2011 - Kuala Lumpur, Malaysia
Duration: 19 Jul 201120 Jul 2011

Publication series

NameProceedings of the 3rd Asia Symposium on Quality Electronic Design, ASQED 2011

Conference

Conference3rd Asia Symposium on Quality Electronic Design, ASQED 2011
Country/TerritoryMalaysia
CityKuala Lumpur
Period19/07/1120/07/11

Keywords

  • Integrated circuit noise
  • SPICE
  • circuit reliability
  • digital circuits
  • thermal noise

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