Register Requirement Minimization of Fixed-Depth Pipelines for Streaming Data Applications

Thomas Goldbrunner; Nguyen Anh Vu Doan; Diogo Pocas; Thomas Wild; Andreas Herkersdorf

doi:10.1109/SOCC46988.2019.1570548393

Register Requirement Minimization of Fixed-Depth Pipelines for Streaming Data Applications

Thomas Goldbrunner, Nguyen Anh Vu Doan, Diogo Pocas, Thomas Wild, Andreas Herkersdorf

Chair of Integrated Systems

Technical University of Munich

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

We present a method that can be used to map control/data flow graphs into fixed-depth pipelines targeted at FPGA design. The main objective for the design is to reduce the register resources which are needed to forward data within the processing pipeline. We show that these requirements can be reduced by appropriate task scheduling. Starting from an intuitive network flow based scheduling approach, we develop a linear programming model of the task scheduling problem. This allows us to efficiently create schedules which are provably optimal with regard to the objective of minimal register usage.

Original language	English
Title of host publication	Proceedings - 32nd IEEE International System on Chip Conference, SOCC 2019
Editors	Danella Zhao, Arindam Basu, Magdy Bayoumi, Gwee Bah Hwee, Ge Tong, Ramalingam Sridhar
Publisher	IEEE Computer Society
Pages	406-411
Number of pages	6
ISBN (Electronic)	9781728134826
DOIs	https://doi.org/10.1109/SOCC46988.2019.1570548393
State	Published - Sep 2019
Event	32nd IEEE International System on Chip Conference, SOCC 2019 - Singapore, Singapore Duration: 3 Sep 2019 → 6 Sep 2019

Publication series

Name	International System on Chip Conference
Volume	2019-September
ISSN (Print)	2164-1676
ISSN (Electronic)	2164-1706

Conference

Conference	32nd IEEE International System on Chip Conference, SOCC 2019
Country/Territory	Singapore
City	Singapore
Period	3/09/19 → 6/09/19

Access to Document

10.1109/SOCC46988.2019.1570548393

Cite this

Goldbrunner, T., Doan, N. A. V., Pocas, D., Wild, T., & Herkersdorf, A. (2019). Register Requirement Minimization of Fixed-Depth Pipelines for Streaming Data Applications. In D. Zhao, A. Basu, M. Bayoumi, G. B. Hwee, G. Tong, & R. Sridhar (Eds.), Proceedings - 32nd IEEE International System on Chip Conference, SOCC 2019 (pp. 406-411). Article 9088030 (International System on Chip Conference; Vol. 2019-September). IEEE Computer Society. https://doi.org/10.1109/SOCC46988.2019.1570548393

Goldbrunner, Thomas ; Doan, Nguyen Anh Vu ; Pocas, Diogo et al. / Register Requirement Minimization of Fixed-Depth Pipelines for Streaming Data Applications. Proceedings - 32nd IEEE International System on Chip Conference, SOCC 2019. editor / Danella Zhao ; Arindam Basu ; Magdy Bayoumi ; Gwee Bah Hwee ; Ge Tong ; Ramalingam Sridhar. IEEE Computer Society, 2019. pp. 406-411 (International System on Chip Conference).

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title = "Register Requirement Minimization of Fixed-Depth Pipelines for Streaming Data Applications",

abstract = "We present a method that can be used to map control/data flow graphs into fixed-depth pipelines targeted at FPGA design. The main objective for the design is to reduce the register resources which are needed to forward data within the processing pipeline. We show that these requirements can be reduced by appropriate task scheduling. Starting from an intuitive network flow based scheduling approach, we develop a linear programming model of the task scheduling problem. This allows us to efficiently create schedules which are provably optimal with regard to the objective of minimal register usage.",

author = "Thomas Goldbrunner and Doan, {Nguyen Anh Vu} and Diogo Pocas and Thomas Wild and Andreas Herkersdorf",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 32nd IEEE International System on Chip Conference, SOCC 2019 ; Conference date: 03-09-2019 Through 06-09-2019",

year = "2019",

month = sep,

doi = "10.1109/SOCC46988.2019.1570548393",

language = "English",

series = "International System on Chip Conference",

publisher = "IEEE Computer Society",

pages = "406--411",

editor = "Danella Zhao and Arindam Basu and Magdy Bayoumi and Hwee, {Gwee Bah} and Ge Tong and Ramalingam Sridhar",

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Goldbrunner, T, Doan, NAV, Pocas, D, Wild, T & Herkersdorf, A 2019, Register Requirement Minimization of Fixed-Depth Pipelines for Streaming Data Applications. in D Zhao, A Basu, M Bayoumi, GB Hwee, G Tong & R Sridhar (eds), Proceedings - 32nd IEEE International System on Chip Conference, SOCC 2019., 9088030, International System on Chip Conference, vol. 2019-September, IEEE Computer Society, pp. 406-411, 32nd IEEE International System on Chip Conference, SOCC 2019, Singapore, Singapore, 3/09/19. https://doi.org/10.1109/SOCC46988.2019.1570548393

Register Requirement Minimization of Fixed-Depth Pipelines for Streaming Data Applications. / Goldbrunner, Thomas; Doan, Nguyen Anh Vu; Pocas, Diogo et al.
Proceedings - 32nd IEEE International System on Chip Conference, SOCC 2019. ed. / Danella Zhao; Arindam Basu; Magdy Bayoumi; Gwee Bah Hwee; Ge Tong; Ramalingam Sridhar. IEEE Computer Society, 2019. p. 406-411 9088030 (International System on Chip Conference; Vol. 2019-September).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - We present a method that can be used to map control/data flow graphs into fixed-depth pipelines targeted at FPGA design. The main objective for the design is to reduce the register resources which are needed to forward data within the processing pipeline. We show that these requirements can be reduced by appropriate task scheduling. Starting from an intuitive network flow based scheduling approach, we develop a linear programming model of the task scheduling problem. This allows us to efficiently create schedules which are provably optimal with regard to the objective of minimal register usage.

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Goldbrunner T, Doan NAV, Pocas D, Wild T, Herkersdorf A. Register Requirement Minimization of Fixed-Depth Pipelines for Streaming Data Applications. In Zhao D, Basu A, Bayoumi M, Hwee GB, Tong G, Sridhar R, editors, Proceedings - 32nd IEEE International System on Chip Conference, SOCC 2019. IEEE Computer Society. 2019. p. 406-411. 9088030. (International System on Chip Conference). doi: 10.1109/SOCC46988.2019.1570548393

Register Requirement Minimization of Fixed-Depth Pipelines for Streaming Data Applications

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