TY - GEN
T1 - Refining task specifications using model checking
AU - Yeolekar, Anand
AU - Metta, Ravindra
AU - Venkatesh, R.
AU - Chakraborty, Samarjit
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2019/1/9
Y1 - 2019/1/9
N2 - The problem of schedulability analysis, i.e., determining whether a given task set meets its deadline constraints, has been extensively studied in the real-time systems literature. However, if a task set is not schedulable, then the schedulability analysis results using known techniques (such as utilization-based tests) offer little insight into which task parameters could be changed or refined, in order to make the task set schedulable. To address this problem, we encode the schedulability analysis problem as an equivalent model checking problem. By analyzing the counterexamples reported by the model checker, we discover subsets of values of task parameters that lead to timing violations. We propose a procedure that iteratively refines the task specification by rejecting these subsets, thereby converging towards schedulability. We believe that this approach would be useful for timing debugging of real-time systems, which has received relatively less attention in the literature, especially given its practical relevance.
AB - The problem of schedulability analysis, i.e., determining whether a given task set meets its deadline constraints, has been extensively studied in the real-time systems literature. However, if a task set is not schedulable, then the schedulability analysis results using known techniques (such as utilization-based tests) offer little insight into which task parameters could be changed or refined, in order to make the task set schedulable. To address this problem, we encode the schedulability analysis problem as an equivalent model checking problem. By analyzing the counterexamples reported by the model checker, we discover subsets of values of task parameters that lead to timing violations. We propose a procedure that iteratively refines the task specification by rejecting these subsets, thereby converging towards schedulability. We believe that this approach would be useful for timing debugging of real-time systems, which has received relatively less attention in the literature, especially given its practical relevance.
KW - Abstraction
KW - Model checking
KW - Real-time-systems
KW - Refienment
KW - Schedulability
KW - Timing-debugging
UR - https://www.scopus.com/pages/publications/85061783289
U2 - 10.1109/RTCSA.2018.00030
DO - 10.1109/RTCSA.2018.00030
M3 - Conference contribution
AN - SCOPUS:85061783289
T3 - Proceedings - 2018 IEEE 24th International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2018
SP - 185
EP - 191
BT - Proceedings - 2018 IEEE 24th International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 24th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2018
Y2 - 29 August 2018 through 31 August 2018
ER -