Reduction of the energy consumption in adiabatic gates by optimal transistor sizing

Keyphrases

• Positive Feedback 100%
• Energy Consumption 100%
• Transistor 100%
• Transistor Sizing 100%
• Adiabatic Logic 100%
• Design Rules 66%
• Energy Saving 66%
• Static CMOS 33%
• Design Centering 33%
• Energy Dissipation 33%
• Operating Frequency 33%
• N-channel 33%
• CMOS Technology 33%
• P-channel 33%
• 1-bit Full Adder 33%
• Charging Path 33%
• Logic Inverter 33%
• Complex Gates 33%

Engineering

• Design Rule 100%
• Channel Transistor 100%
• Energy Dissipation 50%
• Operating Frequency 50%
• Inverter 50%