Reduction of the energy consumption in adiabatic gates by optimal transistor sizing

Jürgen Fischer, Ettore Amirante, Francesco Randazzo, Giuseppe Iannaccone, Doris Schmitt-Landsiedel

Research output: Chapter in Book/Report/Conference proceedingChapterpeer-review

8 Scopus citations

Abstract

Positive Feedback Adiabatic Logic (PFAL) with minimal dimensioned transistors can save energy compared to static CMOS up to an operating frequency f = 200MHz. In this work the impact of transistor sizing is discussed, and design rules are analytically derived and confirmed by simulations. The increase of the p-channel transistor width can significantly reduce the resistance of the charging path decreasing the energy dissipation of the PFAL inverter by a factor of 2. In more complex gates a further design rule for the sizing of the n-channel transistors is proposed. Simulations of a PFAL 1-bit full adder show that the energy consumption can be reduced by additional 10% and energy savings can be achieved beyond f = 1GHz in a 0.13μm CMOS technology. The results are validated through the use of the design centering tool 'WiCkeD' [1].

Original languageEnglish
Title of host publicationLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
EditorsJorge Juan Chico, Enrico Macii
PublisherSpringer Verlag
Pages309-318
Number of pages10
ISBN (Electronic)3540200746, 9783540200741
DOIs
StatePublished - 2003

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume2799
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

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