@inbook{31571b3e2ac44ce7905ac775e69280d0,
title = "Reduction of the energy consumption in adiabatic gates by optimal transistor sizing",
abstract = "Positive Feedback Adiabatic Logic (PFAL) with minimal dimensioned transistors can save energy compared to static CMOS up to an operating frequency f = 200MHz. In this work the impact of transistor sizing is discussed, and design rules are analytically derived and confirmed by simulations. The increase of the p-channel transistor width can significantly reduce the resistance of the charging path decreasing the energy dissipation of the PFAL inverter by a factor of 2. In more complex gates a further design rule for the sizing of the n-channel transistors is proposed. Simulations of a PFAL 1-bit full adder show that the energy consumption can be reduced by additional 10% and energy savings can be achieved beyond f = 1GHz in a 0.13μm CMOS technology. The results are validated through the use of the design centering tool 'WiCkeD' [1].",
author = "J{\"u}rgen Fischer and Ettore Amirante and Francesco Randazzo and Giuseppe Iannaccone and Doris Schmitt-Landsiedel",
year = "2003",
doi = "10.1007/978-3-540-39762-5_37",
language = "English",
series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",
publisher = "Springer Verlag",
pages = "309--318",
editor = "Chico, {Jorge Juan} and Enrico Macii",
booktitle = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",
}