@inproceedings{6e04835fe45a43cfaed2892a0f6250d9,
title = "Reconfigurable PUFs for FPGA-based SoCs",
abstract = "Implementing Physically Unclonable Functions (PUFs) on FPGAs is quite inefficient in terms of resource usage. Many logic and routing resources that could serve as entropy sources remain unused. We introduce a method that uses the partial reconfiguration ability of modern FPGAs as a way to maximize the entropy that can be extracted out of a logic block. Different implementations and types of PUFs can be reprogrammed on the same logic blocks and each of their outputs used as an individual partial key. We show with a first implementation that up to six PUFs can be used on the same logic block on a Xilinx Zynq. The correlation between the PUF outputs remains very small, so that the area needed for the same length of PUF response can be shrunk up to 83%.",
keywords = "FPGA, Partial Reconfiguration, Physically Unclonable Functions (PUFs), RO-based PUF, SoC",
author = "Stefan Gehrer and Georg Sigl",
note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 14th International Symposium on Integrated Circuits, ISIC 2014 ; Conference date: 10-12-2014 Through 12-12-2014",
year = "2015",
month = feb,
day = "2",
doi = "10.1109/ISICIR.2014.7029535",
language = "English",
series = "Proceedings of the 14th International Symposium on Integrated Circuits, ISIC 2014",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "140--143",
booktitle = "Proceedings of the 14th International Symposium on Integrated Circuits, ISIC 2014",
}