Re-writing HDL descriptions for line-aware synthesis of reversible circuits

Reversible computing is a promising research field due to its applications in several emerging technologies. Accordingly, several approaches for the design of reversible circuits have been introduced - including solutions realizing functionality provided in terms of hardware description languages. Their main drawback is, however, that they require a substantial amountof additional circuit lines. While some solutions addressing this problem have been proposed in the past, the contribution of the respectively given HDL code to this drawback has hardly been considered yet. In this work, we are considering this problem from this angle: Observations have been conductedwhich, eventually, led to a set of re-writing rules for a line-aware synthesis of reversible circuits from HDL descriptions. Case studies show the benefits of these rules - in total, substantial reductions in the number of circuit lines have been observed.