PSION: Combining logical topology and physical layout optimization for wavelength-routed ONoCs

Alexandre Truppel, Tsun Ming Tseng, Davide Bertozzi, José Carlos Alves, Ulf Schlichtmann

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

11 Scopus citations

Abstract

Optical Networks-on-Chip (ONoCs) are a promising solution for high-performance multi-core integration with better latency and bandwidth than traditional Electrical NoCs. Wavelength-routed ONoCs (WRONoCs) offer yet additional performance guarantees. However, WRONoC design presents new EDA challenges which have not yet been fully addressed. So far, most topology analysis is abstract, i.e., overlooks layout concerns, while for layout the tools available perform Place & Route (P&R) but no topology optimization. Thus, a need arises for a novel optimization method combining both aspects of WRONoC design. In this paper such a method, PSION, is laid out. When compared to the state-of-the-art design procedure, results show a 1.8× reduction in maximum optical insertion loss.

Original languageEnglish
Title of host publicationISPD 2019 - Proceedings of the 2019 International Symposium on Physical Design
PublisherAssociation for Computing Machinery
Pages49-56
Number of pages8
ISBN (Electronic)9781450362535
DOIs
StatePublished - 4 Apr 2019
Event2019 ACM International Symposium on Physical Design, ISPD 2019 - San Francisco, United States
Duration: 14 Apr 201917 Apr 2019

Publication series

NameProceedings of the International Symposium on Physical Design

Conference

Conference2019 ACM International Symposium on Physical Design, ISPD 2019
Country/TerritoryUnited States
CitySan Francisco
Period14/04/1917/04/19

Keywords

  • Design optimization
  • Optical networks-on-chip
  • Physical layout
  • Placement & routing
  • Silicon photonics

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