PSION 2: Optimizing Physical Layout of Wavelength-Routed ONoCs for Laser Power Reduction

Optical Networks-on-Chip (ONoCs) are becoming increasingly attractive for intra-chip communications due to their low power-per-bit requirements and high bandwidth. Wavelength-Routed ONoCs (WRONoCs), a subtype of ONoCs, further reduce network latency. Recently, tools to design WRONoCs have been developed, but these tools are still incomplete as they do not yet consider key design aspects such as the type of laser source used and the impact of the laser Power Distribution Network (PDN) on the laser power consumption. In this work we propose the first design automation tool to combine awareness of both on-chip and off-chip lasers with optimization of both the logical topology and the physical layout of WRONoCs for application-specific designs. Compared to previous works, the incorporation of the type of laser and the PDN into the optimization process combined with a new Generic Routing Unit (GRU) placement method leads to a laser power reduction of up to 20%.