Protocol merging: A VHDL-based method for clock cycle minimizing and protocol preserving scheduling of IO-operations

W. Ecker; M. Glesner; A. Vombach

Protocol merging: A VHDL-based method for clock cycle minimizing and protocol preserving scheduling of IO-operations

W. Ecker, M. Glesner, A. Vombach

Siemens AG

Research output: Contribution to conference › Paper › peer-review

3 Scopus citations

Abstract

This paper presents a new algorithm for clock cycle minimizing and protocol preserving scheduling of input and output operations. The algorithm relies on the possibility to overlap protocols at different ports in time without changing the behavior. It merges the operations required for complete protocols and allows thus for a compact schedule of a set of correlated protocols. Both, input and scheduled output for subsequent High-Level- and RT-Synthesis use VHDL for description.

Original language	English
Pages	624-629
Number of pages	6
State	Published - 1994
Externally published	Yes
Event	Proceedings of the 1994 European Design Automation Conference - Grenoble, Fr Duration: 19 Sep 1994 → 23 Sep 1994

Conference

Conference	Proceedings of the 1994 European Design Automation Conference
City	Grenoble, Fr
Period	19/09/94 → 23/09/94

Cite this

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title = "Protocol merging: A VHDL-based method for clock cycle minimizing and protocol preserving scheduling of IO-operations",

abstract = "This paper presents a new algorithm for clock cycle minimizing and protocol preserving scheduling of input and output operations. The algorithm relies on the possibility to overlap protocols at different ports in time without changing the behavior. It merges the operations required for complete protocols and allows thus for a compact schedule of a set of correlated protocols. Both, input and scheduled output for subsequent High-Level- and RT-Synthesis use VHDL for description.",

author = "W. Ecker and M. Glesner and A. Vombach",

year = "1994",

language = "English",

pages = "624--629",

note = "Proceedings of the 1994 European Design Automation Conference ; Conference date: 19-09-1994 Through 23-09-1994",

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T2 - Proceedings of the 1994 European Design Automation Conference

AU - Ecker, W.

AU - Glesner, M.

AU - Vombach, A.

PY - 1994

Y1 - 1994

N2 - This paper presents a new algorithm for clock cycle minimizing and protocol preserving scheduling of input and output operations. The algorithm relies on the possibility to overlap protocols at different ports in time without changing the behavior. It merges the operations required for complete protocols and allows thus for a compact schedule of a set of correlated protocols. Both, input and scheduled output for subsequent High-Level- and RT-Synthesis use VHDL for description.

AB - This paper presents a new algorithm for clock cycle minimizing and protocol preserving scheduling of input and output operations. The algorithm relies on the possibility to overlap protocols at different ports in time without changing the behavior. It merges the operations required for complete protocols and allows thus for a compact schedule of a set of correlated protocols. Both, input and scheduled output for subsequent High-Level- and RT-Synthesis use VHDL for description.

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M3 - Paper

AN - SCOPUS:0028713292

SP - 624

EP - 629

Y2 - 19 September 1994 through 23 September 1994

ER -

Protocol merging: A VHDL-based method for clock cycle minimizing and protocol preserving scheduling of IO-operations

Abstract

Conference

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