Protection switching schemes and mapping strategies for fail-operational hard real-time NoCs

Max Koenen, Nguyen Anh Vu Doan, Thomas Wild, Andreas Herkersdorf

Research output: Contribution to journalArticlepeer-review


Communication infrastructures designed for mixed-critical MPSoCs must provide isolation of traffic, hard real-time guarantees, and fault-tolerance. In previous work, we proposed the combination of protection-switching with a hybrid Time-Division-Multiplexed (TDM) and packet-switched Network-on-Chip (NoC) to achieve all three goals. In this paper, we present an FPGA implementation of such a NoC with all its features. We give synthesis results for the hybrid NoC, including the network interface, and show that our router uses over 32% fewer LUTs and registers than a competitive state-of-the-art router for mixed-critical MPSoC. We then explore different channel and task mapping strategies for critical applications which use protection switching and evaluate the effect these mappings have on the best-effort (BE) traffic in the system. Results show, that spreading out the critical traffic rather than naively dividing the system in critical and non-critical application domains is advantageous or even necessary in many cases and can allow for up to 13% more BE traffic. We give a comprehensive trade-off analysis of three protection switching schemes—1:n, 1:1, and 1+1—and show that 1+1 protection has less than half the worst case latency for critical traffic that 1:n and 1:1 protection have. At the same time, 1+1 protection, on average, only causes a 1.18% earlier saturation rate for BE traffic, which we consider to be affordable. We conclude that 1+1 protection is ideally suited for use in mixed-critical systems with high safety requirements.

Original languageEnglish
Article number104385
JournalMicroprocessors and Microsystems
StatePublished - Nov 2021


  • Fail-operational
  • Hybrid NoC
  • Mapping
  • Mixed-critical MPSoC
  • Protection switching


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