TY - GEN
T1 - Processor-in-the Loop Test and Experimental Validations for developed Nine level PV Inverter using High Performance ARM-STM32F407
AU - Fekkak, Bouazza
AU - Loukriz, Abdelhamid
AU - Kennel, Ralph
AU - Azoug, Hakim
AU - Kouzou, Abdellah
AU - Abdelrahem, Mohamed
AU - Mohamed-Seghir, Mostefa
AU - Belmili, Hocine
AU - Menaa, Mohamed
N1 - Publisher Copyright:
© 2021 IEEE.
PY - 2021
Y1 - 2021
N2 - In this paper a Single-Phase nine level inverter based on conventional single-phase H-bridge topology is proposed. It is dedicated to be used for ensuring the connection of single AC load to photovoltaic system. The proposed inverter system features less of switches number and a new auxiliary switches conception. Hence, it gives better voltage regulation, smooth operation and efficient yield compared to multi-level inverters. The proposed inverter topology is capable of producing nine levels of output voltage levels. This inverter is firstly simulated under MATLAB/Simulink software, thereafter, co-simulated using the Processor-in-the-loop (PIL) technique. Secondly, the proposed inverter is designed and tested experimentally. The inverter control is implemented on the high-speed ARM-STM32F407 board. Based on the obtained results, it can be seen clearly that co-simulation results are matching experimental results, which proves the validity of the proposed multi-level inverter. This topology can be extended for more number of phases and levels.
AB - In this paper a Single-Phase nine level inverter based on conventional single-phase H-bridge topology is proposed. It is dedicated to be used for ensuring the connection of single AC load to photovoltaic system. The proposed inverter system features less of switches number and a new auxiliary switches conception. Hence, it gives better voltage regulation, smooth operation and efficient yield compared to multi-level inverters. The proposed inverter topology is capable of producing nine levels of output voltage levels. This inverter is firstly simulated under MATLAB/Simulink software, thereafter, co-simulated using the Processor-in-the-loop (PIL) technique. Secondly, the proposed inverter is designed and tested experimentally. The inverter control is implemented on the high-speed ARM-STM32F407 board. Based on the obtained results, it can be seen clearly that co-simulation results are matching experimental results, which proves the validity of the proposed multi-level inverter. This topology can be extended for more number of phases and levels.
KW - Multi-level inverter
KW - PIL testing
KW - Semiconductor power devices
KW - THD. STM32F407 Board
UR - http://www.scopus.com/inward/record.url?scp=85125779603&partnerID=8YFLogxK
U2 - 10.1109/SPEC52827.2021.9709452
DO - 10.1109/SPEC52827.2021.9709452
M3 - Conference contribution
AN - SCOPUS:85125779603
T3 - 2021 IEEE Southern Power Electronics Conference, SPEC 2021
BT - 2021 IEEE Southern Power Electronics Conference, SPEC 2021
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2021 IEEE Southern Power Electronics Conference, SPEC 2021
Y2 - 6 December 2021 through 9 December 2021
ER -
