Predictable Memory Bandwidth Regulation for DynamIQ Arm Systems

Modern real-time embedded systems increasingly rely on Arm-based Multiprocessor System-on-Chip (MPSoC) architectures to support demanding applications, such as AI workloads and high-speed control systems. To mitigate interference among co-running applications and enforce predictable behavior, software memory bandwidth regulation strategies based on hardware performance counters have been proposed to manage concurrent memory accesses among CPUs. However, such mechanisms (e.g., MemGuard, MemPol) have been mostly evaluated on previous generations of 64-bit Arm systems, i.e., Cortex-A53, A57, or A72. Newer Arm MPSoCs, featuring clusters of Cortex-A55, A76, and A78 cores, introduce (i) the Arm DynamIQ Shared Unit (DSU), (ii) additional cache levels, and (iii) new memory controllers optimized to manage high-bandwidth transactions from accelerators (e.g., GPUs, TPUs). Extending software-based memory bandwidth regulation strategies to newer Arm cores is non-trivial and requires careful characterization of the newly introduced performance counters and the achievable worst-case memory bandwidth (sustainable memory bandwidth). This paper systematically investigates software-based memory bandwidth regulation on DSU-equipped Arm MPSoCs, using the Rockchip RK3588 and NVIDIA AGX Orin as two representative platforms. We empirically evaluate the impact of the new memory hierarchy on sustainable memory bandwidth and the accuracy of performance monitoring counters. We derive updated memory bandwidth regulation models and assess their behavior when applied to MemGuard and MemPol. Our results show that software-based memory bandwidth regulation strategies can be successfully applied to newer platforms. However, the different selection of performance counters might result in pessimistic regulation models.