TY - GEN
T1 - PowerPruning
T2 - 60th ACM/IEEE Design Automation Conference, DAC 2023
AU - Petri, Richard
AU - Zhang, Grace Li
AU - Chen, Yiran
AU - Schlichtmann, Ulf
AU - Li, Bing
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - Deep neural networks (DNNs) have been successfully applied in various fields. A major challenge of deploying DNNs, especially on edge devices, is power consumption, due to the large number of multiply-and-accumulate (MAC) operations. To address this challenge, we propose PowerPruning, a novel method to reduce power consumption in digital neural network accelerators by selecting weights that lead to less power consumption in MAC operations. In addition, the timing characteristics of the selected weights together with all activation transitions are evaluated. The weights and activations that lead to small delays are further selected. Consequently, the maximum delay of the sensitized circuit paths in the MAC units is reduced even without modifying MAC units, which thus allows a flexible scaling of supply voltage to reduce power consumption further. Together with retraining, the proposed method can reduce power consumption of DNNs on hardware by up to 73.9% with only a slight accuracy loss.
AB - Deep neural networks (DNNs) have been successfully applied in various fields. A major challenge of deploying DNNs, especially on edge devices, is power consumption, due to the large number of multiply-and-accumulate (MAC) operations. To address this challenge, we propose PowerPruning, a novel method to reduce power consumption in digital neural network accelerators by selecting weights that lead to less power consumption in MAC operations. In addition, the timing characteristics of the selected weights together with all activation transitions are evaluated. The weights and activations that lead to small delays are further selected. Consequently, the maximum delay of the sensitized circuit paths in the MAC units is reduced even without modifying MAC units, which thus allows a flexible scaling of supply voltage to reduce power consumption further. Together with retraining, the proposed method can reduce power consumption of DNNs on hardware by up to 73.9% with only a slight accuracy loss.
UR - http://www.scopus.com/inward/record.url?scp=85173109095&partnerID=8YFLogxK
U2 - 10.1109/DAC56929.2023.10247868
DO - 10.1109/DAC56929.2023.10247868
M3 - Conference contribution
AN - SCOPUS:85173109095
T3 - Proceedings - Design Automation Conference
BT - 2023 60th ACM/IEEE Design Automation Conference, DAC 2023
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 9 July 2023 through 13 July 2023
ER -