Power crisis in SoC design: Strategies for constructing low-power, high-performance SoC designs

K. Brock; C. Edwards; R. Lannoo; U. Schlichtmann; A. Domic; J. Benkoski; D. Overhauser; M. Kliment

doi:10.1109/DATE.2002.998352

Power crisis in SoC design: Strategies for constructing low-power, high-performance SoC designs

K. Brock, C. Edwards, R. Lannoo, U. Schlichtmann, A. Domic, J. Benkoski, D. Overhauser, M. Kliment

Research output: Contribution to journal › Conference article › peer-review

1 Scopus citations

Abstract

This special panel session brings together several leading technologists to discuss the challenges and solutions in constructing SoC designs that achieve their performance goals within a very tight power budget. These challenges are addressed from the often conflicting perspectives of semiconductor design teams and commercial solutions providers of EDA construction tools, EDA analysis tools and semiconductor IP (SIP).

Original language	English
Article number	998352
Pages (from-to)	538
Number of pages	1
Journal	Proceedings -Design, Automation and Test in Europe, DATE
DOIs	https://doi.org/10.1109/DATE.2002.998352
State	Published - 2002
Externally published	Yes
Event	2002 Design, Automation and Test in Europe Conference and Exhibition, DATE 2002 - Paris, France Duration: 4 Mar 2002 → 8 Mar 2002

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10.1109/DATE.2002.998352

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abstract = "This special panel session brings together several leading technologists to discuss the challenges and solutions in constructing SoC designs that achieve their performance goals within a very tight power budget. These challenges are addressed from the often conflicting perspectives of semiconductor design teams and commercial solutions providers of EDA construction tools, EDA analysis tools and semiconductor IP (SIP).",

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AU - Benkoski, J.

AU - Overhauser, D.

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Power crisis in SoC design: Strategies for constructing low-power, high-performance SoC designs

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