Power-clock-gating in adiabatischen logikschaltungen

To minimize dynamic losses in static CMOS circuits, Clock-Gating ist used to disconnect inactive parts of a system from the clock signal. Leakage losses become more dominant in new technologies, which are reduced by Power-Gating. Adiabatic Logic uses a clocked power supply, thus Power- and Clock-Gating can be achived using only one switch. As the switch raises the dissipated energy in on-state, a major concern is the choice and design of the switch topology. In this paper the basics of Power-Clock-Gating (PCG) in adiabatic logic are described, considerations about the choice of a switch topology are made and design rules for the switch are presented. Further, the influences of PCG on the oscillator are shown.