Posynomial delay models for optimisation-based transistor sizing in digital CMOS VLSI circuits

Numerical optimisation of VLSI circuits evolves as an important tool to achieve short design times for full custom digital MOS circuits. For optimising critical path delays, accurate modeling of signal delay is of special importance. We will present accurate gate level delay time models for CMOS logic circuits. The computation speed improvement of delay calculation is at least two orders of magnitude. Circuit elements can be inverters, M- input- NAND and NOR- gates and CMOS transfer-gates. The new delay models include input waveform effects, which might contribute significantly to gate delay. The models are easy to compute.