Platform-based testbench generation

R. Henftling; A. Zinn; M. Bauer; W. Ecker; M. Zambaldi

doi:10.1109/DATE.2003.1253741

Platform-based testbench generation

R. Henftling
, A. Zinn
, M. Bauer
, W. Ecker
, M. Zambaldi

Infineon Technologies AG

Research output: Contribution to journal › Conference article › peer-review

5 Scopus citations

Abstract

This paper presents a new technology that accelerates system verification. In a real life example, we achieved a speed-up of a factor of about 5000. The key for this speed-up is a configurable, synthesizable testbench architecture, which can be completely mapped to emulators or FPGAs. Exploiting generic controllers and re-using protocol-specific stimuli generators combined with topology and microprogram generation is responsible for almost zero overhead compared to behavioral testbenches.

Original language	English
Article number	1253741
Pages (from-to)	1038-1043
Number of pages	6
Journal	Proceedings -Design, Automation and Test in Europe, DATE
DOIs	https://doi.org/10.1109/DATE.2003.1253741
State	Published - 2003
Externally published	Yes
Event	Design, Automation and Test in Europe Conference and Exhibition, DATE 2003 - Munich, Germany Duration: 3 Mar 2003 → 7 Mar 2003

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10.1109/DATE.2003.1253741

Cite this

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AU - Ecker, W.

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JO - Proceedings -Design, Automation and Test in Europe, DATE

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Platform-based testbench generation

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