TY - GEN
T1 - PieceTimer
T2 - 35th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2016
AU - Zhang, Grace Li
AU - Li, Bing
AU - Schlichtmann, Ulf
N1 - Publisher Copyright:
© 2016 ACM.
PY - 2016/11/7
Y1 - 2016/11/7
N2 - In static timing analysis, clock-to-q delays of flip-flops are considered as constants. Setup times and hold times are characterized separately and also used as constants. The characterized delays, setup times and hold times, are applied in timing analysis independently to verify the performance of circuits. In reality, however, clock-to-q delays of flip-flops depend on both setup and hold times. Instead of being constants, these delays change with respect to different setup/hold time combinations. Consequently, the simple abstraction of setup/hold times and constant clock-to-q delays introduces inaccuracy in timing analysis. In this paper, we propose a holistic method to consider the relation between clock-to-q delays and setup/hold time combinations with a piecewise linear model. The result is more accurate than that of traditional timing analysis, and the incorporation of the interdependency between clock-to-q delays, setup times and hold times may also improve circuit performance.
AB - In static timing analysis, clock-to-q delays of flip-flops are considered as constants. Setup times and hold times are characterized separately and also used as constants. The characterized delays, setup times and hold times, are applied in timing analysis independently to verify the performance of circuits. In reality, however, clock-to-q delays of flip-flops depend on both setup and hold times. Instead of being constants, these delays change with respect to different setup/hold time combinations. Consequently, the simple abstraction of setup/hold times and constant clock-to-q delays introduces inaccuracy in timing analysis. In this paper, we propose a holistic method to consider the relation between clock-to-q delays and setup/hold time combinations with a piecewise linear model. The result is more accurate than that of traditional timing analysis, and the incorporation of the interdependency between clock-to-q delays, setup times and hold times may also improve circuit performance.
UR - http://www.scopus.com/inward/record.url?scp=85001022246&partnerID=8YFLogxK
U2 - 10.1145/2966986.2967064
DO - 10.1145/2966986.2967064
M3 - Conference contribution
AN - SCOPUS:85001022246
T3 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
BT - 2016 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2016
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 7 November 2016 through 10 November 2016
ER -