Abstract
In this work an analytical first principle model for the current noise of poly-Si layers is presented and compared with measured data. For these resistors frequently used in analog CMOS applications the observed noise is much higher than predicted by the models used in circuit simulation. For the first time, dependencies on specific processing parameters such as doping or deposition techniques are investigated and explained. Moreover, deviations in the noise behavior of small size resistors are described satisfactorily. Guidelines for analog circuit design and a model suitable for circuit simulation are presented.
Original language | English |
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Pages (from-to) | 89-92 |
Number of pages | 4 |
Journal | Technical Digest - International Electron Devices Meeting |
State | Published - 1998 |
Externally published | Yes |
Event | Proceedings of the 1998 IEEE International Electron Devices Meeting - San Francisco, CA, USA Duration: 6 Dec 1998 → 9 Dec 1998 |