Physical configuration on-line visualization of Xilinx Virtex-II FPGAs

Michael Hübner; Lars Braun; Jürgen Becker; Christopher Claus; Walter Stechele

doi:10.1109/ISVLSI.2007.83

Physical configuration on-line visualization of Xilinx Virtex-II FPGAs

Michael Hübner, Lars Braun, Jürgen Becker, Christopher Claus, Walter Stechele

Chair of Integrated Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

11 Scopus citations

Abstract

Xilinx Virtex-II / Virtex-II Pro FPGAs provide the possibility of partial and dynamic run-time reconfiguration. This feature can be used in adaptive systems providing the possibility to adapt to application requirements by exchanging parts of the hardware while other parts stay operative. This computing in time and space and many other fine grained adjustments within the architectures, opens new dimensions for electronic system design as well as for novel scheduling mechanisms based on well established graph-based algorithms in comparison to pure microprocessor based electronic systems. However, at the moment it is not possible to visualize the physical configuration of the chip and the manifold possibilities of manipulations on the device. This feature allows to demonstrate the system's behavior and helps to debug final integrated reconfigurable systems. This paper presents an approach to the system integration of an autonomously working on-line visualization stand alone IP-Core integrated on Xilinx Virtex-II and Virtex-II Pro FPGAs.

Original language	English
Title of host publication	Proceedings - IEEE Computer Society Annual Symposium on VLSI
Subtitle of host publication	Emerging VLSI Technologies and Architectures
Pages	41-46
Number of pages	6
DOIs	https://doi.org/10.1109/ISVLSI.2007.83
State	Published - 2007
Event	IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07 - Porto Alegre, Brazil Duration: 9 Mar 2007 → 11 Mar 2007

Publication series

Name	Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures

Conference

Conference	IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07
Country/Territory	Brazil
City	Porto Alegre
Period	9/03/07 → 11/03/07

Keywords

Dynamic reconfiguration
FPGA
On-line visualization

Access to Document

10.1109/ISVLSI.2007.83

Cite this

Hübner, M., Braun, L., Becker, J., Claus, C., & Stechele, W. (2007). Physical configuration on-line visualization of Xilinx Virtex-II FPGAs. In Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (pp. 41-46). Article 4208892 (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures). https://doi.org/10.1109/ISVLSI.2007.83

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title = "Physical configuration on-line visualization of Xilinx Virtex-II FPGAs",

abstract = "Xilinx Virtex-II / Virtex-II Pro FPGAs provide the possibility of partial and dynamic run-time reconfiguration. This feature can be used in adaptive systems providing the possibility to adapt to application requirements by exchanging parts of the hardware while other parts stay operative. This computing in time and space and many other fine grained adjustments within the architectures, opens new dimensions for electronic system design as well as for novel scheduling mechanisms based on well established graph-based algorithms in comparison to pure microprocessor based electronic systems. However, at the moment it is not possible to visualize the physical configuration of the chip and the manifold possibilities of manipulations on the device. This feature allows to demonstrate the system's behavior and helps to debug final integrated reconfigurable systems. This paper presents an approach to the system integration of an autonomously working on-line visualization stand alone IP-Core integrated on Xilinx Virtex-II and Virtex-II Pro FPGAs.",

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Hübner, M, Braun, L, Becker, J, Claus, C & Stechele, W 2007, Physical configuration on-line visualization of Xilinx Virtex-II FPGAs. in Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures., 4208892, Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, pp. 41-46, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07, Porto Alegre, Brazil, 9/03/07. https://doi.org/10.1109/ISVLSI.2007.83

Physical configuration on-line visualization of Xilinx Virtex-II FPGAs. / Hübner, Michael; Braun, Lars; Becker, Jürgen et al.
Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures. 2007. p. 41-46 4208892 (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Braun, Lars

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AU - Claus, Christopher

AU - Stechele, Walter

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N2 - Xilinx Virtex-II / Virtex-II Pro FPGAs provide the possibility of partial and dynamic run-time reconfiguration. This feature can be used in adaptive systems providing the possibility to adapt to application requirements by exchanging parts of the hardware while other parts stay operative. This computing in time and space and many other fine grained adjustments within the architectures, opens new dimensions for electronic system design as well as for novel scheduling mechanisms based on well established graph-based algorithms in comparison to pure microprocessor based electronic systems. However, at the moment it is not possible to visualize the physical configuration of the chip and the manifold possibilities of manipulations on the device. This feature allows to demonstrate the system's behavior and helps to debug final integrated reconfigurable systems. This paper presents an approach to the system integration of an autonomously working on-line visualization stand alone IP-Core integrated on Xilinx Virtex-II and Virtex-II Pro FPGAs.

AB - Xilinx Virtex-II / Virtex-II Pro FPGAs provide the possibility of partial and dynamic run-time reconfiguration. This feature can be used in adaptive systems providing the possibility to adapt to application requirements by exchanging parts of the hardware while other parts stay operative. This computing in time and space and many other fine grained adjustments within the architectures, opens new dimensions for electronic system design as well as for novel scheduling mechanisms based on well established graph-based algorithms in comparison to pure microprocessor based electronic systems. However, at the moment it is not possible to visualize the physical configuration of the chip and the manifold possibilities of manipulations on the device. This feature allows to demonstrate the system's behavior and helps to debug final integrated reconfigurable systems. This paper presents an approach to the system integration of an autonomously working on-line visualization stand alone IP-Core integrated on Xilinx Virtex-II and Virtex-II Pro FPGAs.

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Hübner M, Braun L, Becker J, Claus C, Stechele W. Physical configuration on-line visualization of Xilinx Virtex-II FPGAs. In Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures. 2007. p. 41-46. 4208892. (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures). doi: 10.1109/ISVLSI.2007.83

Physical configuration on-line visualization of Xilinx Virtex-II FPGAs

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