Performance optimization of 3D multigrid on hierarchical memory architectures

Markus Kowarschik, Ulrich Rüde, Nils Thürey, Christian Weiß

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

7 Scopus citations

Abstract

Today's computer architectures employ fast cache memories in order to hide both the low main memory bandwidth and the latency of main memory accesses, which is slow in contrast to the floating- point performance of the CPUs. Efficient program execution can only be achieved, if the codes respect the hierarchical memory design. Iterative methods for linear systems of equations are characterized by successive sweeps over data sets, which are much too large to fit in cache. Standard implementations of these methods thus do not perform efficiently on cache-based machines. In this paper we present techniques to enhance the cache utilization of multigrid methods on regular mesh structures in 3D as well as various performance results. Most of these techniques extend our previous work on 2D problems.

Original languageEnglish
Title of host publicationApplied Parallel Computing
Subtitle of host publicationAdvanced Scientific Computing - 6th International Conference, PARA 2002, Proceedings
EditorsJuha Fagerholm, Juha Haataja, Jari Jarvinen, Mikko Lyly, Peter Raback, Ville Savolainen
PublisherSpringer Verlag
Pages307-316
Number of pages10
ISBN (Print)354043786X, 9783540437864
DOIs
StatePublished - 2002
Externally publishedYes
Event6th International Conference on Applied Parallel Computing, PARA 2002 - Espoo, Finland
Duration: 15 Jun 200218 Jun 2002

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume2367
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Conference

Conference6th International Conference on Applied Parallel Computing, PARA 2002
Country/TerritoryFinland
CityEspoo
Period15/06/0218/06/02

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