Performance investigation of semiconductor devices using commutation-speed based methodology for the application of boost power factor correction

In this paper, behavioral approach has been adopted for the calculation of total power losses that has been further used to derive an analytical model for the conduction and switching losses in a boost Power Factor Correction (PFC) stage of an On-board Charger (OBC). Detailed investigation of power losses can help in finding out ways to improve efficiency and for this purpose, commutation-speed based methodology has been used to split total power losses into their root causes. This gives opportunity to find the impact that an individual part creates on total losses which can serve as a starting point for efficiency improvement. For the analysis, two devices (IGBT with Si diode and IGBT with SiC diode) are used in the considered topology of PFC and a reduction of 40% was calculated when SiC diode was used instead of Si with the same IGBT. Hence it was found that the implemented method proves to be significantly useful in the optimization of efficiency.