TY - JOUR
T1 - Performance evaluation of network processor architectures
T2 - Combining simulation with analytical estimation
AU - Chakraborty, Samarjit
AU - Künzli, Simon
AU - Thiele, Lothar
AU - Herkersdorf, Andreas
AU - Sagmeister, Patricia
N1 - Funding Information:
The work presented in this paper was partly supported by the National Competence Center in Research on Mobile Information and Communication Systems (NCCR-MICS), a center supported by the Swiss National Science Foundation under grant number 5005-67322. The authors are also thankful to the two anonymous reviewers, whose suggestions greatly improved the contents of this paper.
PY - 2003/4/5
Y1 - 2003/4/5
N2 - Simulation was combined with analytic estimation to study performance evaluation of network processor architectures. A scheme for the design space exploration of the systems-on-a-chip (SoC) architecture was proposed. The design process was separated into multiple stages, each having a different level of abstraction.
AB - Simulation was combined with analytic estimation to study performance evaluation of network processor architectures. A scheme for the design space exploration of the systems-on-a-chip (SoC) architecture was proposed. The design process was separated into multiple stages, each having a different level of abstraction.
KW - Application-specific instruction set processors
KW - High-performance routers
KW - Network processors
KW - Performance analysis
UR - http://www.scopus.com/inward/record.url?scp=0037420692&partnerID=8YFLogxK
U2 - 10.1016/S1389-1286(02)00454-1
DO - 10.1016/S1389-1286(02)00454-1
M3 - Article
AN - SCOPUS:0037420692
SN - 1389-1286
VL - 41
SP - 641
EP - 665
JO - Computer Networks
JF - Computer Networks
IS - 5
ER -