TY - GEN
T1 - Out-of-plane NML modeling and architectural exploration
AU - Cairo, F.
AU - Turvani, G.
AU - Riente, F.
AU - Vacca, M.
AU - Gamm, S. Breitkreutz V.
AU - Becherer, M.
AU - Graziano, M.
AU - Zamboni, M.
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015
Y1 - 2015
N2 - One of the most innovative solutions studied as an alternative technology to CMOS transistors is represented by NanoMagnetic Logic (NML). It exhibits remarkable characteristics that overcome some intrinsic limitations of CMOS as low power consumption and the possibility to merge logic and memory in the same device. We present the design of a full adder entirely based on single domain out-of-plane nanomagnetic logic (pNML). We propose different solutions of the same circuit which allow us to obtain the best performance in terms of occupied area and timing. We modeled, using VHDL (VHSIC Hardware Description Language), the pNML basic elements and then we performed micromagnetic simulations to demonstrate the correct operation of the circuits.
AB - One of the most innovative solutions studied as an alternative technology to CMOS transistors is represented by NanoMagnetic Logic (NML). It exhibits remarkable characteristics that overcome some intrinsic limitations of CMOS as low power consumption and the possibility to merge logic and memory in the same device. We present the design of a full adder entirely based on single domain out-of-plane nanomagnetic logic (pNML). We propose different solutions of the same circuit which allow us to obtain the best performance in terms of occupied area and timing. We modeled, using VHDL (VHSIC Hardware Description Language), the pNML basic elements and then we performed micromagnetic simulations to demonstrate the correct operation of the circuits.
KW - Field Coupled Computing
KW - Low Power
KW - MQCA
KW - Perpendicular Nanomagnetic Logic (pNML)
UR - http://www.scopus.com/inward/record.url?scp=84964394203&partnerID=8YFLogxK
U2 - 10.1109/NANO.2015.7388798
DO - 10.1109/NANO.2015.7388798
M3 - Conference contribution
AN - SCOPUS:84964394203
T3 - IEEE-NANO 2015 - 15th International Conference on Nanotechnology
SP - 1037
EP - 1040
BT - IEEE-NANO 2015 - 15th International Conference on Nanotechnology
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 15th IEEE International Conference on Nanotechnology, IEEE-NANO 2015
Y2 - 27 July 2015 through 30 July 2015
ER -