Optimizing latency and CPU load in packet processing systems

Paul Emmerich; Daniel Raumer; Alexander Beifuss; Lukas Erlacher; Florian Wohlfart; Torsten M. Runge; Sebastian Gallenmuller; Georg Carle

doi:10.1109/SPECTS.2015.7285275

Optimizing latency and CPU load in packet processing systems

Paul Emmerich, Daniel Raumer, Alexander Beifuss, Lukas Erlacher, Florian Wohlfart, Torsten M. Runge, Sebastian Gallenmuller, Georg Carle

Informatics 8 - Chair of Network Architectures and Services

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

22 Scopus citations

Abstract

High-speed network cards supporting 10 or 40GbE (Gigabit Ethernet) are available today. Software frameworks for high-speed packet reception and transmission were created to exhaust the performance of these cards. However, these frameworks are not applicable as general-purpose solution. Thus, it is necessary to revisit general purpose network IO software that was designed more than a decade ago. In standard Linux settings, connectivity between applications and physical networks happens via the New API (NAPI). This motivated us to investigate how underlying NIC drivers can be adapted to improve latency in combination with the Linux NAPI. Based on testbed measurements, we propose an optimized algorithm for the NIC driver to dynamically adapt the Interrupt Throttling Rate (ITR). We implemented the algorithm and evaluated it with latency and throughput measurements based on the Linux module of Open vSwitch that operates on top of the NAPI. Our measurements show that our new ITR algorithm improves the packet latency without affecting the CPU load as much as other solutions.

Original language	English
Title of host publication	Proceedings of the 2015 International Symposium on Performance Evaluation of Computer and Telecommunication Systems, SPECTS 2015 - Part of SummerSim 2015 Multiconference
Editors	Franco Davoli, Malamati Louta, Imadeldin Mahgoub, Jose Saldana, Mohammad S. Obaidat, Jose L Marzo, Joel Rodrigues
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781510810600
DOIs	https://doi.org/10.1109/SPECTS.2015.7285275
State	Published - 30 Sep 2015
Event	2015 International Symposium on Performance Evaluation of Computer and Telecommunication Systems, SPECTS 2015 - Chicago, United States Duration: 26 Jul 2015 → 29 Jul 2015

Publication series

Name	Proceedings of the 2015 International Symposium on Performance Evaluation of Computer and Telecommunication Systems, SPECTS 2015 - Part of SummerSim 2015 Multiconference

Conference

Conference	2015 International Symposium on Performance Evaluation of Computer and Telecommunication Systems, SPECTS 2015
Country/Territory	United States
City	Chicago
Period	26/07/15 → 29/07/15

Keywords

ITR
Linux
NAPI
NIC driver
commodity hardware
packet latency
packet processing

Access to Document

10.1109/SPECTS.2015.7285275

Cite this

Emmerich, P., Raumer, D., Beifuss, A., Erlacher, L., Wohlfart, F., Runge, T. M., Gallenmuller, S., & Carle, G. (2015). Optimizing latency and CPU load in packet processing systems. In F. Davoli, M. Louta, I. Mahgoub, J. Saldana, M. S. Obaidat, J. L. Marzo, & J. Rodrigues (Eds.), Proceedings of the 2015 International Symposium on Performance Evaluation of Computer and Telecommunication Systems, SPECTS 2015 - Part of SummerSim 2015 Multiconference Article 7285275 (Proceedings of the 2015 International Symposium on Performance Evaluation of Computer and Telecommunication Systems, SPECTS 2015 - Part of SummerSim 2015 Multiconference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SPECTS.2015.7285275

Emmerich, Paul ; Raumer, Daniel ; Beifuss, Alexander et al. / Optimizing latency and CPU load in packet processing systems. Proceedings of the 2015 International Symposium on Performance Evaluation of Computer and Telecommunication Systems, SPECTS 2015 - Part of SummerSim 2015 Multiconference. editor / Franco Davoli ; Malamati Louta ; Imadeldin Mahgoub ; Jose Saldana ; Mohammad S. Obaidat ; Jose L Marzo ; Joel Rodrigues. Institute of Electrical and Electronics Engineers Inc., 2015. (Proceedings of the 2015 International Symposium on Performance Evaluation of Computer and Telecommunication Systems, SPECTS 2015 - Part of SummerSim 2015 Multiconference).

@inproceedings{a3ec87049b1f4815b410bec7c9092e0d,

title = "Optimizing latency and CPU load in packet processing systems",

abstract = "High-speed network cards supporting 10 or 40GbE (Gigabit Ethernet) are available today. Software frameworks for high-speed packet reception and transmission were created to exhaust the performance of these cards. However, these frameworks are not applicable as general-purpose solution. Thus, it is necessary to revisit general purpose network IO software that was designed more than a decade ago. In standard Linux settings, connectivity between applications and physical networks happens via the New API (NAPI). This motivated us to investigate how underlying NIC drivers can be adapted to improve latency in combination with the Linux NAPI. Based on testbed measurements, we propose an optimized algorithm for the NIC driver to dynamically adapt the Interrupt Throttling Rate (ITR). We implemented the algorithm and evaluated it with latency and throughput measurements based on the Linux module of Open vSwitch that operates on top of the NAPI. Our measurements show that our new ITR algorithm improves the packet latency without affecting the CPU load as much as other solutions.",

keywords = "ITR, Linux, NAPI, NIC driver, commodity hardware, packet latency, packet processing",

author = "Paul Emmerich and Daniel Raumer and Alexander Beifuss and Lukas Erlacher and Florian Wohlfart and Runge, {Torsten M.} and Sebastian Gallenmuller and Georg Carle",

note = "Publisher Copyright: {\textcopyright} 2015 Society for Modeling and Simulation International.; 2015 International Symposium on Performance Evaluation of Computer and Telecommunication Systems, SPECTS 2015 ; Conference date: 26-07-2015 Through 29-07-2015",

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Emmerich, P, Raumer, D, Beifuss, A, Erlacher, L, Wohlfart, F, Runge, TM, Gallenmuller, S & Carle, G 2015, Optimizing latency and CPU load in packet processing systems. in F Davoli, M Louta, I Mahgoub, J Saldana, MS Obaidat, JL Marzo & J Rodrigues (eds), Proceedings of the 2015 International Symposium on Performance Evaluation of Computer and Telecommunication Systems, SPECTS 2015 - Part of SummerSim 2015 Multiconference., 7285275, Proceedings of the 2015 International Symposium on Performance Evaluation of Computer and Telecommunication Systems, SPECTS 2015 - Part of SummerSim 2015 Multiconference, Institute of Electrical and Electronics Engineers Inc., 2015 International Symposium on Performance Evaluation of Computer and Telecommunication Systems, SPECTS 2015, Chicago, United States, 26/07/15. https://doi.org/10.1109/SPECTS.2015.7285275

Optimizing latency and CPU load in packet processing systems. / Emmerich, Paul; Raumer, Daniel; Beifuss, Alexander et al.
Proceedings of the 2015 International Symposium on Performance Evaluation of Computer and Telecommunication Systems, SPECTS 2015 - Part of SummerSim 2015 Multiconference. ed. / Franco Davoli; Malamati Louta; Imadeldin Mahgoub; Jose Saldana; Mohammad S. Obaidat; Jose L Marzo; Joel Rodrigues. Institute of Electrical and Electronics Engineers Inc., 2015. 7285275 (Proceedings of the 2015 International Symposium on Performance Evaluation of Computer and Telecommunication Systems, SPECTS 2015 - Part of SummerSim 2015 Multiconference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Emmerich, Paul

AU - Raumer, Daniel

AU - Beifuss, Alexander

AU - Erlacher, Lukas

AU - Wohlfart, Florian

AU - Runge, Torsten M.

AU - Gallenmuller, Sebastian

AU - Carle, Georg

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N2 - High-speed network cards supporting 10 or 40GbE (Gigabit Ethernet) are available today. Software frameworks for high-speed packet reception and transmission were created to exhaust the performance of these cards. However, these frameworks are not applicable as general-purpose solution. Thus, it is necessary to revisit general purpose network IO software that was designed more than a decade ago. In standard Linux settings, connectivity between applications and physical networks happens via the New API (NAPI). This motivated us to investigate how underlying NIC drivers can be adapted to improve latency in combination with the Linux NAPI. Based on testbed measurements, we propose an optimized algorithm for the NIC driver to dynamically adapt the Interrupt Throttling Rate (ITR). We implemented the algorithm and evaluated it with latency and throughput measurements based on the Linux module of Open vSwitch that operates on top of the NAPI. Our measurements show that our new ITR algorithm improves the packet latency without affecting the CPU load as much as other solutions.

AB - High-speed network cards supporting 10 or 40GbE (Gigabit Ethernet) are available today. Software frameworks for high-speed packet reception and transmission were created to exhaust the performance of these cards. However, these frameworks are not applicable as general-purpose solution. Thus, it is necessary to revisit general purpose network IO software that was designed more than a decade ago. In standard Linux settings, connectivity between applications and physical networks happens via the New API (NAPI). This motivated us to investigate how underlying NIC drivers can be adapted to improve latency in combination with the Linux NAPI. Based on testbed measurements, we propose an optimized algorithm for the NIC driver to dynamically adapt the Interrupt Throttling Rate (ITR). We implemented the algorithm and evaluated it with latency and throughput measurements based on the Linux module of Open vSwitch that operates on top of the NAPI. Our measurements show that our new ITR algorithm improves the packet latency without affecting the CPU load as much as other solutions.

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KW - Linux

KW - NAPI

KW - NIC driver

KW - commodity hardware

KW - packet latency

KW - packet processing

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M3 - Conference contribution

AN - SCOPUS:84992121790

T3 - Proceedings of the 2015 International Symposium on Performance Evaluation of Computer and Telecommunication Systems, SPECTS 2015 - Part of SummerSim 2015 Multiconference

BT - Proceedings of the 2015 International Symposium on Performance Evaluation of Computer and Telecommunication Systems, SPECTS 2015 - Part of SummerSim 2015 Multiconference

A2 - Davoli, Franco

A2 - Louta, Malamati

A2 - Mahgoub, Imadeldin

A2 - Saldana, Jose

A2 - Obaidat, Mohammad S.

A2 - Marzo, Jose L

A2 - Rodrigues, Joel

PB - Institute of Electrical and Electronics Engineers Inc.

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ER -

Emmerich P, Raumer D, Beifuss A, Erlacher L, Wohlfart F, Runge TM et al. Optimizing latency and CPU load in packet processing systems. In Davoli F, Louta M, Mahgoub I, Saldana J, Obaidat MS, Marzo JL, Rodrigues J, editors, Proceedings of the 2015 International Symposium on Performance Evaluation of Computer and Telecommunication Systems, SPECTS 2015 - Part of SummerSim 2015 Multiconference. Institute of Electrical and Electronics Engineers Inc. 2015. 7285275. (Proceedings of the 2015 International Symposium on Performance Evaluation of Computer and Telecommunication Systems, SPECTS 2015 - Part of SummerSim 2015 Multiconference). doi: 10.1109/SPECTS.2015.7285275

Optimizing latency and CPU load in packet processing systems

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