Optimized Detection of Marginal Defects in Standard Cells Using Unsupervised Learning

Karthik Pandaram, Hussam Amrouch, Ilia Polian

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Marginal defects, such as high-resistance short or low-resistance open defects, are hard to detect by conventional pass-fail test methods because their manifestations are practically indistinguishable from the effects of regular variations. However, their coverage is essential for circuits with high-quality requirements and/or when early-life failures are a concern. In this paper, we propose an alternative detection concept based on evaluating several parametric responses of a circuit against a machine learning (ML) model. We use a 14nm FinFET transistor model validated against industrial measurements. We show that high detection performance is possible even when unsupervised learning that does not consider defective behavior is used; to this end, the procedure is generic. Moreover, an AUC score of over 0.96 is achieved when only measurements from a single voltage level are utilized, in contrast to earlier work. We also present a procedure to select a reduced set of test sequences, achieving an improvement of 50% reduction with a limited impact on detection performance.

Original languageEnglish
Title of host publicationProceedings of the 2024 IEEE 33rd Asian Test Symposium, ATS 2024
PublisherIEEE Computer Society
ISBN (Electronic)9798331529161
DOIs
StatePublished - 2024
Event33rd IEEE Asian Test Symposium, ATS 2024 - Ahmedabad, India
Duration: 17 Dec 202420 Dec 2024

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735

Conference

Conference33rd IEEE Asian Test Symposium, ATS 2024
Country/TerritoryIndia
CityAhmedabad
Period17/12/2420/12/24

Keywords

  • Machine learning for testing
  • Small delay faults
  • Unsupervised learning

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