TY - GEN
T1 - Optimized Detection of Marginal Defects in Standard Cells Using Unsupervised Learning
AU - Pandaram, Karthik
AU - Amrouch, Hussam
AU - Polian, Ilia
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - Marginal defects, such as high-resistance short or low-resistance open defects, are hard to detect by conventional pass-fail test methods because their manifestations are practically indistinguishable from the effects of regular variations. However, their coverage is essential for circuits with high-quality requirements and/or when early-life failures are a concern. In this paper, we propose an alternative detection concept based on evaluating several parametric responses of a circuit against a machine learning (ML) model. We use a 14nm FinFET transistor model validated against industrial measurements. We show that high detection performance is possible even when unsupervised learning that does not consider defective behavior is used; to this end, the procedure is generic. Moreover, an AUC score of over 0.96 is achieved when only measurements from a single voltage level are utilized, in contrast to earlier work. We also present a procedure to select a reduced set of test sequences, achieving an improvement of 50% reduction with a limited impact on detection performance.
AB - Marginal defects, such as high-resistance short or low-resistance open defects, are hard to detect by conventional pass-fail test methods because their manifestations are practically indistinguishable from the effects of regular variations. However, their coverage is essential for circuits with high-quality requirements and/or when early-life failures are a concern. In this paper, we propose an alternative detection concept based on evaluating several parametric responses of a circuit against a machine learning (ML) model. We use a 14nm FinFET transistor model validated against industrial measurements. We show that high detection performance is possible even when unsupervised learning that does not consider defective behavior is used; to this end, the procedure is generic. Moreover, an AUC score of over 0.96 is achieved when only measurements from a single voltage level are utilized, in contrast to earlier work. We also present a procedure to select a reduced set of test sequences, achieving an improvement of 50% reduction with a limited impact on detection performance.
KW - Machine learning for testing
KW - Small delay faults
KW - Unsupervised learning
UR - http://www.scopus.com/inward/record.url?scp=105001132857&partnerID=8YFLogxK
U2 - 10.1109/ATS64447.2024.10915423
DO - 10.1109/ATS64447.2024.10915423
M3 - Conference contribution
AN - SCOPUS:105001132857
T3 - Proceedings of the Asian Test Symposium
BT - Proceedings of the 2024 IEEE 33rd Asian Test Symposium, ATS 2024
PB - IEEE Computer Society
T2 - 33rd IEEE Asian Test Symposium, ATS 2024
Y2 - 17 December 2024 through 20 December 2024
ER -