TY - GEN
T1 - Optimization potential of CMOS power by wire spacing
AU - Zuber, Paul
AU - Müller, Florian Helmut
AU - Stechele, Walter
PY - 2005
Y1 - 2005
N2 - In this work, we identify the power-optimal wire spacing as a geometric program. Its solution is a vector of individual distances between the wires. To quantify the optimization potential by this method we model the output of a grid based router with a set of parallel wires. A comparison of the power values before and after geometric optimization shows that the optimization potential lies well in the two digit percent zone for a representative circuit model in a 130nm process.
AB - In this work, we identify the power-optimal wire spacing as a geometric program. Its solution is a vector of individual distances between the wires. To quantify the optimization potential by this method we model the output of a grid based router with a set of parallel wires. A comparison of the power values before and after geometric optimization shows that the optimization potential lies well in the two digit percent zone for a representative circuit model in a 130nm process.
UR - https://www.scopus.com/pages/publications/84874241934
M3 - Conference contribution
AN - SCOPUS:84874241934
SN - 3885793962
SN - 9783885793960
T3 - INFORMATIK 2005 - Informatik LIVE!, Beitrage der 35. Jahrestagung der Gesellschaft fur Informatik e.V. (GI)
SP - 344
EP - 348
BT - INFORMATIK 2005 - Informatik LIVE!, Beitrage der 35. Jahrestagung der Gesellschaft fur Informatik e.V. (GI)
T2 - 35th Jahrestagung der Gesellschaft fur Informatik e.V. (GI): Informatik LIVE!, INFORMATIK 200535th Annual Conference of the German Informatics Society (GI): Informatics LIVE!,INFORMATIK 2005
Y2 - 19 September 2005 through 22 September 2005
ER -