Optimization of SC ΣΔ modulators based on worst-case-aware Pareto-optimal fronts

Jun Zou; Helmut Graeb; Daniel Mueller; Ulf Schlichtmann

doi:10.1109/CICC.2007.4405805

Optimization of SC ΣΔ modulators based on worst-case-aware Pareto-optimal fronts

Jun Zou
, Helmut Graeb
, Daniel Mueller
, Ulf Schlichtmann

Chair of Electronic Design Automation

Technical University of Munich
Qimonda AG i IN

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

This paper presents an optimization method for switched-capacitor σ-δ modulators. The SNR performance is maximized while considering the performance capability of the critical building block, i.e. The Op Amp. Performance space exploration is applied to find the feasible region of the building block's performance, which is represented by a Pareto-optimal front. Through worst-case analysis on design points of the nominal Pareto front, a worst-case-aware Pareto-optimal front can be computed. The maximized SNR and the corresponding yield will be presented. The proposed optimization process is efficient and can be accomplished in some hours.

Original language	English
Title of host publication	Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	607-610
Number of pages	4
ISBN (Electronic)	1424407869, 9781424407866
DOIs	https://doi.org/10.1109/CICC.2007.4405805
State	Published - 2007
Event	29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007 - San Jose, United States Duration: 16 Sep 2007 → 19 Sep 2007

Publication series

Name	Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Conference

Conference	29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007
Country/Territory	United States
City	San Jose
Period	16/09/07 → 19/09/07

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10.1109/CICC.2007.4405805

Cite this

Zou, J., Graeb, H., Mueller, D., & Schlichtmann, U. (2007). Optimization of SC ΣΔ modulators based on worst-case-aware Pareto-optimal fronts. In Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007 (pp. 607-610). Article 4405805 (Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2007.4405805

Zou, Jun ; Graeb, Helmut ; Mueller, Daniel et al. / Optimization of SC ΣΔ modulators based on worst-case-aware Pareto-optimal fronts. Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007. Institute of Electrical and Electronics Engineers Inc., 2007. pp. 607-610 (Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007).

@inproceedings{ec6ed085c9134e64999115c5ec93d9ed,

title = "Optimization of SC ΣΔ modulators based on worst-case-aware Pareto-optimal fronts",

abstract = "This paper presents an optimization method for switched-capacitor σ-δ modulators. The SNR performance is maximized while considering the performance capability of the critical building block, i.e. The Op Amp. Performance space exploration is applied to find the feasible region of the building block's performance, which is represented by a Pareto-optimal front. Through worst-case analysis on design points of the nominal Pareto front, a worst-case-aware Pareto-optimal front can be computed. The maximized SNR and the corresponding yield will be presented. The proposed optimization process is efficient and can be accomplished in some hours.",

author = "Jun Zou and Helmut Graeb and Daniel Mueller and Ulf Schlichtmann",

note = "Publisher Copyright: {\textcopyright} 2007 IEEE.; 29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007 ; Conference date: 16-09-2007 Through 19-09-2007",

year = "2007",

doi = "10.1109/CICC.2007.4405805",

language = "English",

series = "Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007",

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}

Zou, J, Graeb, H, Mueller, D & Schlichtmann, U 2007, Optimization of SC ΣΔ modulators based on worst-case-aware Pareto-optimal fronts. in Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007., 4405805, Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007, Institute of Electrical and Electronics Engineers Inc., pp. 607-610, 29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007, San Jose, United States, 16/09/07. https://doi.org/10.1109/CICC.2007.4405805

Optimization of SC ΣΔ modulators based on worst-case-aware Pareto-optimal fronts. / Zou, Jun; Graeb, Helmut; Mueller, Daniel et al.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007. Institute of Electrical and Electronics Engineers Inc., 2007. p. 607-610 4405805 (Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Optimization of SC ΣΔ modulators based on worst-case-aware Pareto-optimal fronts

AU - Zou, Jun

AU - Graeb, Helmut

AU - Mueller, Daniel

AU - Schlichtmann, Ulf

PY - 2007

Y1 - 2007

N2 - This paper presents an optimization method for switched-capacitor σ-δ modulators. The SNR performance is maximized while considering the performance capability of the critical building block, i.e. The Op Amp. Performance space exploration is applied to find the feasible region of the building block's performance, which is represented by a Pareto-optimal front. Through worst-case analysis on design points of the nominal Pareto front, a worst-case-aware Pareto-optimal front can be computed. The maximized SNR and the corresponding yield will be presented. The proposed optimization process is efficient and can be accomplished in some hours.

AB - This paper presents an optimization method for switched-capacitor σ-δ modulators. The SNR performance is maximized while considering the performance capability of the critical building block, i.e. The Op Amp. Performance space exploration is applied to find the feasible region of the building block's performance, which is represented by a Pareto-optimal front. Through worst-case analysis on design points of the nominal Pareto front, a worst-case-aware Pareto-optimal front can be computed. The maximized SNR and the corresponding yield will be presented. The proposed optimization process is efficient and can be accomplished in some hours.

UR - https://www.scopus.com/pages/publications/58149125885

U2 - 10.1109/CICC.2007.4405805

DO - 10.1109/CICC.2007.4405805

M3 - Conference contribution

AN - SCOPUS:58149125885

T3 - Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

SP - 607

EP - 610

BT - Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007

Y2 - 16 September 2007 through 19 September 2007

ER -

Zou J, Graeb H, Mueller D , Schlichtmann U. Optimization of SC ΣΔ modulators based on worst-case-aware Pareto-optimal fronts. In Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007. Institute of Electrical and Electronics Engineers Inc. 2007. p. 607-610. 4405805. (Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007). doi: 10.1109/CICC.2007.4405805

Optimization of SC ΣΔ modulators based on worst-case-aware Pareto-optimal fronts

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