Optimization of LGate for ggNMOS ESD protection devices fabricated on bulk- and SOI- substrates, using process and device simulation

A. I. Deckelmann; G. Wachutka

doi:10.1109/SISPAD.2003.1233684

Optimization of L_Gate for ggNMOS ESD protection devices fabricated on bulk- and SOI- substrates, using process and device simulation

A. I. Deckelmann, G. Wachutka

Computation, Information and Technology

Technical University of Munich

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

The high-current characteristics of ggNMOS fabricated on bulk- as well as on SOI-substrates using a 0.6 μm-CMOS technology have been simulated for different values of the gate length L_Gate. Prior to the simulation, the doping profiles and physical transport parameters were calibrated with reference to measured data. The snapback differential resistance R_spdiff is found to be higher for SOI-devices. Also, an optimum value of L_Gate is determined for the bulk-substrate, yielding a minimum snapback holding voltage V_H. For SOI fabrication, however, VH decreases with shrinking L_Gate. We explain this behavior on the basis of the electrothermal simulation results.

Original language	English
Title of host publication	SISPAD 2003 - 2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	251-254
Number of pages	4
ISBN (Electronic)	0780378261
DOIs	https://doi.org/10.1109/SISPAD.2003.1233684
State	Published - 2003
Event	2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2003 - Boston, United States Duration: 3 Sep 2003 → 5 Sep 2003

Publication series

Name	International Conference on Simulation of Semiconductor Processes and Devices, SISPAD
Volume	2003-January

Conference

Conference	2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2003
Country/Territory	United States
City	Boston
Period	3/09/03 → 5/09/03

Keywords

Calibration
Doping profiles
Electrical resistance measurement
Electrostatic discharge
Electrothermal effects
Fabrication
Physics
Protection
Semiconductor process modeling
Voltage

Access to Document

10.1109/SISPAD.2003.1233684

Cite this

Deckelmann, A. I., & Wachutka, G. (2003). Optimization of L_Gate for ggNMOS ESD protection devices fabricated on bulk- and SOI- substrates, using process and device simulation. In SISPAD 2003 - 2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices (pp. 251-254). Article 1233684 (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD; Vol. 2003-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SISPAD.2003.1233684

Deckelmann, A. I. ; Wachutka, G. / Optimization of L_Gate for ggNMOS ESD protection devices fabricated on bulk- and SOI- substrates, using process and device simulation. SISPAD 2003 - 2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices. Institute of Electrical and Electronics Engineers Inc., 2003. pp. 251-254 (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD).

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title = "Optimization of LGate for ggNMOS ESD protection devices fabricated on bulk- and SOI- substrates, using process and device simulation",

abstract = "The high-current characteristics of ggNMOS fabricated on bulk- as well as on SOI-substrates using a 0.6 μm-CMOS technology have been simulated for different values of the gate length LGate. Prior to the simulation, the doping profiles and physical transport parameters were calibrated with reference to measured data. The snapback differential resistance Rspdiff is found to be higher for SOI-devices. Also, an optimum value of LGate is determined for the bulk-substrate, yielding a minimum snapback holding voltage VH. For SOI fabrication, however, VH decreases with shrinking LGate. We explain this behavior on the basis of the electrothermal simulation results.",

keywords = "Calibration, Doping profiles, Electrical resistance measurement, Electrostatic discharge, Electrothermal effects, Fabrication, Physics, Protection, Semiconductor process modeling, Voltage",

author = "Deckelmann, {A. I.} and G. Wachutka",

note = "Publisher Copyright: {\textcopyright} 2003 IEEE.; 2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2003 ; Conference date: 03-09-2003 Through 05-09-2003",

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doi = "10.1109/SISPAD.2003.1233684",

language = "English",

series = "International Conference on Simulation of Semiconductor Processes and Devices, SISPAD",

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Deckelmann, AI & Wachutka, G 2003, Optimization of L_Gate for ggNMOS ESD protection devices fabricated on bulk- and SOI- substrates, using process and device simulation. in SISPAD 2003 - 2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices., 1233684, International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, vol. 2003-January, Institute of Electrical and Electronics Engineers Inc., pp. 251-254, 2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2003, Boston, United States, 3/09/03. https://doi.org/10.1109/SISPAD.2003.1233684

Optimization of L_Gate for ggNMOS ESD protection devices fabricated on bulk- and SOI- substrates, using process and device simulation. / Deckelmann, A. I.; Wachutka, G.
SISPAD 2003 - 2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices. Institute of Electrical and Electronics Engineers Inc., 2003. p. 251-254 1233684 (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD; Vol. 2003-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - The high-current characteristics of ggNMOS fabricated on bulk- as well as on SOI-substrates using a 0.6 μm-CMOS technology have been simulated for different values of the gate length LGate. Prior to the simulation, the doping profiles and physical transport parameters were calibrated with reference to measured data. The snapback differential resistance Rspdiff is found to be higher for SOI-devices. Also, an optimum value of LGate is determined for the bulk-substrate, yielding a minimum snapback holding voltage VH. For SOI fabrication, however, VH decreases with shrinking LGate. We explain this behavior on the basis of the electrothermal simulation results.

AB - The high-current characteristics of ggNMOS fabricated on bulk- as well as on SOI-substrates using a 0.6 μm-CMOS technology have been simulated for different values of the gate length LGate. Prior to the simulation, the doping profiles and physical transport parameters were calibrated with reference to measured data. The snapback differential resistance Rspdiff is found to be higher for SOI-devices. Also, an optimum value of LGate is determined for the bulk-substrate, yielding a minimum snapback holding voltage VH. For SOI fabrication, however, VH decreases with shrinking LGate. We explain this behavior on the basis of the electrothermal simulation results.

KW - Calibration

KW - Doping profiles

KW - Electrical resistance measurement

KW - Electrostatic discharge

KW - Electrothermal effects

KW - Fabrication

KW - Physics

KW - Protection

KW - Semiconductor process modeling

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BT - SISPAD 2003 - 2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices

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Deckelmann AI, Wachutka G. Optimization of L_Gate for ggNMOS ESD protection devices fabricated on bulk- and SOI- substrates, using process and device simulation. In SISPAD 2003 - 2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices. Institute of Electrical and Electronics Engineers Inc. 2003. p. 251-254. 1233684. (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD). doi: 10.1109/SISPAD.2003.1233684