Optimization of Bit Mapping and Quantized Decoding for Off-the-Shelf Protograph LDPC Codes with Application to IEEE 802.3ca

Fabian Steiner, Gerhard Kramer

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

Protograph-based, off-the-shelf low-density parity-check (LDPC) codes are optimized for higher-order modulation and quantized sum-product decoders. As an example, for the recently proposed LDPC code from the upcoming IEEE 802.3ca standard for passive optical networks (PONs), an optimized mapping of the bit channels originating from bit-metric decoding to the protograph variable nodes gains 0.4 dB and 0.3 dB at a bit-error rate of 10-6 for shaped and uniform signaling, respectively. Furthermore, the clipping value for a quantized sum-product LDPC decoder is optimized via discretized density evolution.

Original languageEnglish
Title of host publication2018 IEEE 10th International Symposium on Turbo Codes and Iterative Information Processing, ISTC 2018
PublisherIEEE Computer Society
ISBN (Electronic)9781538670484
DOIs
StatePublished - 2 Jul 2018
Event10th IEEE International Symposium on Turbo Codes and Iterative Information Processing, ISTC 2018 - Hong Kong, China
Duration: 3 Dec 20187 Dec 2018

Publication series

NameInternational Symposium on Turbo Codes and Iterative Information Processing, ISTC
Volume2018-December
ISSN (Print)2165-4700
ISSN (Electronic)2165-4719

Conference

Conference10th IEEE International Symposium on Turbo Codes and Iterative Information Processing, ISTC 2018
Country/TerritoryChina
CityHong Kong
Period3/12/187/12/18

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