Abstract
A method for architectural evaluation and optimization of regular combinatoric logic structures with replicative circuitry, like e.g. decoders, multiplexers or comparators, is presented. The complete circuitry is modeled by one characteristics signal path where the fan out of the gates and the number of equivalent gates in each stage are taken into account. The device dimensions are optimized with respect to signal delay and area consumption. Posynomial gate level macromodels are used to determine delay and area. So different architectural implementations for a given problem are systematically compared based on optimized solutions.
| Original language | English |
|---|---|
| Pages (from-to) | 69-73 |
| Number of pages | 5 |
| Journal | Microprocessing and Microprogramming |
| Volume | 32 |
| Issue number | 1-5 |
| DOIs | |
| State | Published - Aug 1991 |
| Externally published | Yes |
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