Optimal placement of registers in data paths for low power design

Keyphrases

• Switching Activity 100%
• Glitches 100%
• Retiming 100%
• Optimal Placement 100%
• Low-power Design 100%
• Proposed Methodology 100%
• Probabilistic Approach 50%
• Time Constraints 50%
• Path Delay 50%
• Propagation Delay 50%
• Typical Data 50%
• Combinational Circuits 50%
• Glitch 50%
• Logic Path 50%
• Path Structures 50%

Engineering

• Data Path 100%
• Optimal Placement 100%
• Design Power 100%
• Switching Activity 40%
• Nodes 20%
• Probabilistic Approach 20%
• Combinatorial Circuits 20%
• Propagation Delay 20%

Computer Science

• Low-Power Design 100%
• Switching Activity 100%
• Propagation Delay 50%
• Combinational Circuit 50%
• Timing Constraint 50%
• Probabilistic Approach 50%