Abstract
A method for multiobjective optimization of replicative logic circuitry, like decoders, adders or comparators, is presented. The device dimensions are optimized with respect to signal delay, power dissipation, and area consumption. The fan out of the gates, the number of gates in every stage, and the operation mode of the circuit are taken into account. Posynomial gate-level macromodels are used to determine the circuit performance; therefore, efficient analytical multicriterion optimization techniques can be applied. With the new procedure, different architectural implementations of replicative combinatorial logic circuitry are systematically compared based on optimized device dimensions.
| Original language | English |
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| Pages (from-to) | 2264-2267 |
| Number of pages | 4 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 4 |
| State | Published - 1991 |
| Event | 1991 IEEE International Symposium on Circuits and Systems Part 4 (of 5) - Singapore, Singapore Duration: 11 Jun 1991 → 14 Jun 1991 |