On the relationship between correlation power analysis and the stochastic approach: An ASIC designer perspective

The design and the security verification of side-channel resistant cryptographic hardware often represent an iterative process. This process essentially consists of a detection phase (), where the information leakage is identified and a correction phase (), where design flaws are corrected. Correlation Power Analysis (CPA) and the Stochastic Approach (SA) are two candidate tools to perform the and to support designers in the. However, until now, the relationship between these two tools has not been discussed yet and it is uncertain from a designer point of view, what informative feedback can be gained from these methods, especially when it comes to evaluate high-dimensional leakage models. In this work, we investigate the relationship between CPA and the SA from both a mathematical and empirical point of view. In particular, we demonstrate that the informative feedback provided by the SA is transferable to a linear combination of CPA attacks and discuss the implications of this entanglement, when it comes to pinpoint the high-dimensional leakage of simulated leakage data and simulated power traces of an ASIC implementation of Present.