TY - GEN
T1 - On pinning issues on multicore systems
AU - Trinitis, Carsten
PY - 2009
Y1 - 2009
N2 - In recent years, a trend towards multi-core architectures with a growing number of cores for all standard instruction set architectures can be observed. To utilize the full potential of such novel microprocessor architectures, applications running on them must be efficiently parallelized and carefully analyzed regarding runtime, speedup, and parallel efficiency. With multi-core architectures becoming more and more complex, it is essential to compare available hardware with respect to how efficient an application can run on it. Within this context, several x86 based architectures have been tested. Besides the well known SPEC OMP benchmarks, pinning was also tested for a numerical simulation program based on sparse matrix operations. Benchmark tests were carried out on dual quad core Intel Nehalem based systems as well as on AMD Shanghai based systems. In addition, front side bus based systems, namely a dual quad core Intel Clovertown and a quad six core Intel Dunnington were investigated with respect to pinning.
AB - In recent years, a trend towards multi-core architectures with a growing number of cores for all standard instruction set architectures can be observed. To utilize the full potential of such novel microprocessor architectures, applications running on them must be efficiently parallelized and carefully analyzed regarding runtime, speedup, and parallel efficiency. With multi-core architectures becoming more and more complex, it is essential to compare available hardware with respect to how efficient an application can run on it. Within this context, several x86 based architectures have been tested. Besides the well known SPEC OMP benchmarks, pinning was also tested for a numerical simulation program based on sparse matrix operations. Benchmark tests were carried out on dual quad core Intel Nehalem based systems as well as on AMD Shanghai based systems. In addition, front side bus based systems, namely a dual quad core Intel Clovertown and a quad six core Intel Dunnington were investigated with respect to pinning.
KW - Multi-core
KW - Performance tuning
KW - Pinning
KW - Sparse matrices
KW - Spec omp
KW - Threads
UR - http://www.scopus.com/inward/record.url?scp=70449486000&partnerID=8YFLogxK
U2 - 10.1109/HPCSIM.2009.5192734
DO - 10.1109/HPCSIM.2009.5192734
M3 - Conference contribution
AN - SCOPUS:70449486000
SN - 9781424449071
T3 - Proceedings of the 2009 International Conference on High Performance Computing and Simulation, HPCS 2009
SP - 81
BT - Proceedings of the 2009 International Conference on High Performance Computing and Simulation, HPCS 2009
T2 - 2009 International Conference on High Performance Computing and Simulation, HPCS '09
Y2 - 21 June 2009 through 24 June 2009
ER -