On-line supply voltage scaling based on in situ delay monitoring to adapt for PVTA variations

The presented Pre-Error Adaptive Voltage Scaling (AVS) approach tunes the supply voltage of digital circuits dependent on the present Process, Voltage and Temperature variations as well as Aging (PVTA). By exploiting unused timing margin, produced by state-of-the-art worst-case designs, power consumption is minimized. Timing information of the circuit is obtained by in situ delay monitors (Pre-Error flip-flops), detecting late-arriving signals (pre-errors) in critical paths. Based on the occurrence of pre-errors, the voltage is adjusted by a low-overhead control unit connected to the on-chip voltage regulator. As the voltage is adapted during normal circuit operation (on-line), the randomness of the applied input pattern has to be considered. We developed a Markov chain model, based on transistor level simulations, to describe the resulting statistics of the closed-loop voltage control. With this model, the risk of overcritical voltage reductions and the effect of global and local variations on the closed-loop control can be analyzed. For an arithmetic circuit, synthesized in an industrial 65nm design-flow, an average power saving of 23% (including all overheads) is achieved for very low error rates below 1E-11.