Novel Trade-offs in 5nm FinFET SRAM Arrays at Extreme Low Temperatures

Complementary Metal Oxide Semiconductor (CMOS)-based computing promises drastic improvement in performance at extremely low temperatures (e.g., 77K, 10K). The field of extreme lowtemperature CMOS environment-based computing holds the promise of delivering remarkable enhancements in both performance and power consumption. Static Random-Access Memory (SRAM) plays a major role in determining the performance and efficiency of any processor due to its superior performance and density. This work aims to reveal how extreme low-temperature operations profoundly impact the existing well-known trade-offs in SRAM-based memory arrays. To accomplish this, first, we measure and model the 5nm Fin Field-Effect Transistors (FinFETs) characteristics over a wide temperature range from 300K down to 10K. Next, we develop a framework to perform simulations on the SRAM array by varying the number of rows and columns for examining the influence of leakage current (Ileak), and parasitic effects of Bit-Line (BL) and Word-Line (WL) on the size and performance of the SRAM array under extreme low-temperatures. For a comprehensive analysis, we further investigated the maximum attainable array size, extending our study down to 10K, utilizing three distinct cell types. With the help of SRAM array simulations, we reveal that the maximum array size at extremely low temperatures is limited by WL parasitics instead of Ileak, and the performance of the SRAM is governed by BL and WL parasitics. Additionally, we elucidate the influence of transistor threshold voltage (VTH) engineering on the optimization of the SRAM array at extreme low-temperature environments.