TY - GEN
T1 - Novel approaches to circuit timing
AU - Schlichtmann, Ulf
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/5/29
Y1 - 2018/5/29
N2 - In conventional sequential digital design, flip-flops are used to separate combinational logic gates. Signal propagation across logic gates ends at flip-flops. Accordingly, the minimum clock period is determined by the maximum of combinational delays between flip-flops. This partitioning of combinational logic into stages reduces design complexity significantly. However, in modern high-performance designs where clock frequency is usually pushed to the limit, this strict logic separation by flip-flops sacrifices timing performance. In addition, the simple assumption that all combinational paths work within one clock period makes the task to prevent counterfeiting very challenging, because a netlist extracted from reverse engineering represents all the functional information and can be processed using a standard IC design flow and used to produce chips in different foundries illegally. In this paper, we demonstrate two techniques that loosen the conventional strict separation of logic gates with flip-flops to enhance circuit performance and to reinforce netlist security.
AB - In conventional sequential digital design, flip-flops are used to separate combinational logic gates. Signal propagation across logic gates ends at flip-flops. Accordingly, the minimum clock period is determined by the maximum of combinational delays between flip-flops. This partitioning of combinational logic into stages reduces design complexity significantly. However, in modern high-performance designs where clock frequency is usually pushed to the limit, this strict logic separation by flip-flops sacrifices timing performance. In addition, the simple assumption that all combinational paths work within one clock period makes the task to prevent counterfeiting very challenging, because a netlist extracted from reverse engineering represents all the functional information and can be processed using a standard IC design flow and used to produce chips in different foundries illegally. In this paper, we demonstrate two techniques that loosen the conventional strict separation of logic gates with flip-flops to enhance circuit performance and to reinforce netlist security.
UR - http://www.scopus.com/inward/record.url?scp=85048884412&partnerID=8YFLogxK
U2 - 10.1109/CSTIC.2018.8369325
DO - 10.1109/CSTIC.2018.8369325
M3 - Conference contribution
AN - SCOPUS:85048884412
T3 - China Semiconductor Technology International Conference 2018, CSTIC 2018
SP - 1
EP - 4
BT - China Semiconductor Technology International Conference 2018, CSTIC 2018
A2 - Wu, Hanming
A2 - Song, Peilin
A2 - Lin, Qinghuang
A2 - Wang, Yuchun
A2 - Claeys, Cor
A2 - Lung, Hsiang-Lang
A2 - Zhang, Ying
A2 - Liang, Steve
A2 - Shi, Yiyu
A2 - Huang, Ru
A2 - Guo, Zhen
A2 - Lai, Kafai
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2018 China Semiconductor Technology International Conference, CSTIC 2018
Y2 - 11 March 2018 through 12 March 2018
ER -